4 ms·

MyHDL – Design hardware with Python – Examples

101 points by mr_tyzic 12y ago

xtacy 12y ago
A related project is Chisel, in which you create language using Scala: https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/
- hrjet 12y ago
  Very happy to see both the projects (MyHDL and Chisel). I am not the target audience, but I was once interested in building some thing like this in Scala. What is the uptake of Chisel in the target audience? I have observed that hardware designers that are not familiar with general programming language concepts don't appreciate the benefits of type-safe and object-oriented languages. Heck, even the software developer community is divided over the subject.
- aninhumer 12y ago
  Also Bluespec: http://wiki.bluespec.com/Home/multiplier-example http://wiki.bluespec.com/Home/multiplier-example
ioseph 12y ago
Always great to see new developments in HDLs. It seems there is no synthesis (which is to be expected without vendor support). With 'limited' conversion to VHDL/Verilog, I wonder how useful this is for actual implementation. Also from the site I couldn't find any mention of higher level functionality such as generics, etc.
- mattip 12y ago
  MyHDL is not bad for quick prototyping. The main problem I had was using vendor-supplied libraries in simulation, I needed to completely model the vendor block (timing and input-output) which is quite error prone. OTOH, one of the nice things is the ease of moving from a numpy model of the system to RTL. And using PyPy for running simulations really makes MyHDL hum along quickly [0] [0] http://old.myhdl.org/doku.php/performance http://old.myhdl.org/doku.php/performance
- int19h 12y ago
  SystemC is the C++ equivalent that's been around for a long time. For a project I was working on, I used SystemC just for system-level modelling, it didn't bother me that I couldn't synthesize. To achieve decent clock-rates it would have been a good idea to reimplement the whole thing in "native" Verilog anyway (though my project didn't get that far). What SystemC provided me with is a way to sanity-check my model at the "transaction" level. Pretty cool to see this, and going forward as a roadmap there is much they could borrow from SystemC.
  - jandecaluwe 12y ago
    MyHDL is implemented as a minimalistic pure Python library, which basically means that you can use Python features for modeling - pretty powerful. In addition, it supports conversion of a language subset, so that you can also use it as a synthesizable RTL language. The latter feature is absent from SystemC.
- jandecaluwe 12y ago
  MyHDL has been and is being used for production designs. For parametrizability, you have the full Python power at your disposal. This is also true for conversion, because conversion happens after elaboration of the design.
wyager 12y ago
There is so much potential in open source hardware design. Right now, we are held back by (at best) mediocre tools. We need better HDL software, better synthesis software, better EDA software before we have any hope of widespread use of open source hardware. Imagine if the only compilers available were proprietary compilers locked behind hundreds of pages of licensing requirements and legal bullshit. Open source software would still be in the dark ages. I applaud any effort to advance the open source hardware design toolset.
- hrjet 12y ago
  I think this is where FPGAs might prove very useful. Even if the designs made on FPGAs are small-scale, amateurish or sub-optimal today, they will help develop an ecosystem of tools, including open-source tools, that will ultimately help larger-scale open-source hardware.
  - wyager 12y ago
    The problem with FPGAs is the design software. Have you ever tried to use WebPACK ISE or Quartus? Both of them blow. Terrible UI, terrible design, terrible licensing requirements. We need simple, easy, powerful, and free tools for FPGA development before open source FPGA cores take off.
    - hrjet 12y ago
      I am agreeing with your first point. But I am suggesting an alternative to your second point. When FPGA boards become available to more people, the tools will automatically come. Note that, the open-source tools can be built by software professionals, even though they might be amateurs in hardware design.
      - noselasd 12y ago
        Thee's already cheap ($50 and less) FPGA boards. But all FPGAs are proprietary, there's no available documentation on the internals, the bitstream, and many other things one need to create 3.party/open source tools. And I also suspect they're hard to impossible to reverse engineer.
DanWaterworth 12y ago
I've recently started writing my own HDL as an embedded language within Idris. The idea behind it is that you can take advantage of the rich type system and you have the option to prove theorems about your circuits to gain confidence in them. There are also bindings to picosat, so that you can automatically prove some properties. Here's a snippet of how it looks so far (though things are changing rapidly): lt : BoolOperation op => Vect n v -> Vect n v -> SSA op v v lt [] [] = constOp False lt (x :: xs) (y :: ys) = do nX <- notOp x t1 <- andOp [nX, y] t2 <- xnorOp x y t3 <- lt xs ys t4 <- andOp [t2, t3] orOp [t1, t4]
- simias 12y ago
  That's just combinational logic, how do you implement clocked processes and latches? In my (admittedly limited) experience with hardware design making correct pure combinational logic isn't generally too difficult, it's keeping track of the state and state transitions that's problematic.
  - DanWaterworth 12y ago
    I'm glad you asked. At the moment, only combinational circuits are possible, but I'm working to extend this to synchronous (clocked) circuits. When you need feedback, there will be a combinator that will look something like this: feedback : Vect n Bool -> (Vect i v -> Vect n v -> SSA op v (Vect n v, Vect o v)) -> Vect i v -> SSA op v (Vect o v) This is all up in the air. I'm still working it through. I'm very keen to end up with something that it nice to use, even at the expense of being difficult to implement. I may be getting ahead of myself, but I'd like to have functions that do things like: take a combinational circuit and return a synchronous circuit where the logic is evenly separated (in terms of delay) over n clock cycles.
- aninhumer 12y ago
  I worked on creating a HDL as a DSL in Haskell as my undergraduate project: https://github.com/aninhumer/mantle https://github.com/aninhumer/mantle I haven't touched the code since I graduated last year, and I've had various ideas about how I should restructure it since then. The most interesting part of the project is probably the implementation of guarded channels, which turned out to admit useful Functor and Applicative instances. I hope to start as a PhD student next year working on a new version of the language taking into account what I've learned since then. Most notably, GHC's recursive do-notation sounds like it will be incredibly useful for creating the kind of monadic cyclic graph structures needed for hardware.
sown 12y ago
I like this. I keep saying there's a hardware renaissance near by and I think the wider-spread use of HDL and the like will help along with this.
paraboul 12y ago
Related project : https://github.com/m-labs/migen https://github.com/m-labs/migen
- sanxiyn 12y ago
  Migen is quite different from MyHDL. Migen folks specifically wrote about differences from MyHDL here: https://github.com/m-labs/migen/blob/master/doc/fhdl.rst https://github.com/m-labs/migen/blob/master/doc/fhdl.rst
aprdm 12y ago
I don't know, i've been working with VHDL for 5 years and i don't see how this could be useful. Usually we first develop our algorithms using fixed point math at Matlab, which is a piece of cake. After doing this, developing our VHDL based on Matlab implementation is very straight forward. Python language isn't a very common knowledge for people developing hardware, so they really need to learn a complete new language made to another domain (software) in order to do the same thing! VHDL/Verilog has been used for 30 years and in my opinion will continue to be used for many mores, Python's language structure just doesn't have what's needed to the hardware domain. I see myself wasting a lot of time having to teach our old hardware guys Python and how to think in terms of RTL with a new Language. That's why i didn't try to switch. Remember, most of the engineers working with hardware come from EE background, not CS. They are more familliar with Schematics than C.
- DigitalJack 12y ago
  For design I agree. For verification, software techniques are often used and systemverilog has a lot of growing up to do.
- Igglyboo 12y ago
  This is extremely useful for people with CS backgrounds who want to get into CS. My first dive into VHDL was disasterous, I feel like it would have went much better if I had used something like this with a familiar syntax.

101 points by mr_tyzic 12y ago

xtacy 12y ago

A related project is Chisel, in which you create language using Scala: https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/

hrjet 12y ago
Very happy to see both the projects (MyHDL and Chisel). I am not the target audience, but I was once interested in building some thing like this in Scala. What is the uptake of Chisel in the target audience? I have observed that hardware designers that are not familiar with general programming language concepts don't appreciate the benefits of type-safe and object-oriented languages. Heck, even the software developer community is divided over the subject.
aninhumer 12y ago
Also Bluespec: http://wiki.bluespec.com/Home/multiplier-example http://wiki.bluespec.com/Home/multiplier-example

ioseph 12y ago

Always great to see new developments in HDLs. It seems there is no synthesis (which is to be expected without vendor support). With 'limited' conversion to VHDL/Verilog, I wonder how useful this is for actual implementation. Also from the site I couldn't find any mention of higher level functionality such as generics, etc.

mattip 12y ago
MyHDL is not bad for quick prototyping. The main problem I had was using vendor-supplied libraries in simulation, I needed to completely model the vendor block (timing and input-output) which is quite error prone. OTOH, one of the nice things is the ease of moving from a numpy model of the system to RTL. And using PyPy for running simulations really makes MyHDL hum along quickly [0] [0] http://old.myhdl.org/doku.php/performance http://old.myhdl.org/doku.php/performance
int19h 12y ago
SystemC is the C++ equivalent that's been around for a long time. For a project I was working on, I used SystemC just for system-level modelling, it didn't bother me that I couldn't synthesize. To achieve decent clock-rates it would have been a good idea to reimplement the whole thing in "native" Verilog anyway (though my project didn't get that far). What SystemC provided me with is a way to sanity-check my model at the "transaction" level. Pretty cool to see this, and going forward as a roadmap there is much they could borrow from SystemC.
- jandecaluwe 12y ago
  MyHDL is implemented as a minimalistic pure Python library, which basically means that you can use Python features for modeling - pretty powerful. In addition, it supports conversion of a language subset, so that you can also use it as a synthesizable RTL language. The latter feature is absent from SystemC.
jandecaluwe 12y ago
MyHDL has been and is being used for production designs. For parametrizability, you have the full Python power at your disposal. This is also true for conversion, because conversion happens after elaboration of the design.

wyager 12y ago

There is so much potential in open source hardware design. Right now, we are held back by (at best) mediocre tools. We need better HDL software, better synthesis software, better EDA software before we have any hope of widespread use of open source hardware. Imagine if the only compilers available were proprietary compilers locked behind hundreds of pages of licensing requirements and legal bullshit. Open source software would still be in the dark ages. I applaud any effort to advance the open source hardware design toolset.

hrjet 12y ago
I think this is where FPGAs might prove very useful. Even if the designs made on FPGAs are small-scale, amateurish or sub-optimal today, they will help develop an ecosystem of tools, including open-source tools, that will ultimately help larger-scale open-source hardware.
- wyager 12y ago
  The problem with FPGAs is the design software. Have you ever tried to use WebPACK ISE or Quartus? Both of them blow. Terrible UI, terrible design, terrible licensing requirements. We need simple, easy, powerful, and free tools for FPGA development before open source FPGA cores take off.
  - hrjet 12y ago
    I am agreeing with your first point. But I am suggesting an alternative to your second point. When FPGA boards become available to more people, the tools will automatically come. Note that, the open-source tools can be built by software professionals, even though they might be amateurs in hardware design.
    - noselasd 12y ago
      Thee's already cheap ($50 and less) FPGA boards. But all FPGAs are proprietary, there's no available documentation on the internals, the bitstream, and many other things one need to create 3.party/open source tools. And I also suspect they're hard to impossible to reverse engineer.

DanWaterworth 12y ago

I've recently started writing my own HDL as an embedded language within Idris. The idea behind it is that you can take advantage of the rich type system and you have the option to prove theorems about your circuits to gain confidence in them. There are also bindings to picosat, so that you can automatically prove some properties. Here's a snippet of how it looks so far (though things are changing rapidly): lt : BoolOperation op => Vect n v -> Vect n v -> SSA op v v lt [] [] = constOp False lt (x :: xs) (y :: ys) = do nX <- notOp x t1 <- andOp [nX, y] t2 <- xnorOp x y t3 <- lt xs ys t4 <- andOp [t2, t3] orOp [t1, t4]

simias 12y ago
That's just combinational logic, how do you implement clocked processes and latches? In my (admittedly limited) experience with hardware design making correct pure combinational logic isn't generally too difficult, it's keeping track of the state and state transitions that's problematic.
- DanWaterworth 12y ago
  I'm glad you asked. At the moment, only combinational circuits are possible, but I'm working to extend this to synchronous (clocked) circuits. When you need feedback, there will be a combinator that will look something like this: feedback : Vect n Bool -> (Vect i v -> Vect n v -> SSA op v (Vect n v, Vect o v)) -> Vect i v -> SSA op v (Vect o v) This is all up in the air. I'm still working it through. I'm very keen to end up with something that it nice to use, even at the expense of being difficult to implement. I may be getting ahead of myself, but I'd like to have functions that do things like: take a combinational circuit and return a synchronous circuit where the logic is evenly separated (in terms of delay) over n clock cycles.
aninhumer 12y ago
I worked on creating a HDL as a DSL in Haskell as my undergraduate project: https://github.com/aninhumer/mantle https://github.com/aninhumer/mantle I haven't touched the code since I graduated last year, and I've had various ideas about how I should restructure it since then. The most interesting part of the project is probably the implementation of guarded channels, which turned out to admit useful Functor and Applicative instances. I hope to start as a PhD student next year working on a new version of the language taking into account what I've learned since then. Most notably, GHC's recursive do-notation sounds like it will be incredibly useful for creating the kind of monadic cyclic graph structures needed for hardware.

sown 12y ago

I like this. I keep saying there's a hardware renaissance near by and I think the wider-spread use of HDL and the like will help along with this.

paraboul 12y ago

Related project : https://github.com/m-labs/migen https://github.com/m-labs/migen

sanxiyn 12y ago
Migen is quite different from MyHDL. Migen folks specifically wrote about differences from MyHDL here: https://github.com/m-labs/migen/blob/master/doc/fhdl.rst https://github.com/m-labs/migen/blob/master/doc/fhdl.rst

aprdm 12y ago

I don't know, i've been working with VHDL for 5 years and i don't see how this could be useful. Usually we first develop our algorithms using fixed point math at Matlab, which is a piece of cake. After doing this, developing our VHDL based on Matlab implementation is very straight forward. Python language isn't a very common knowledge for people developing hardware, so they really need to learn a complete new language made to another domain (software) in order to do the same thing! VHDL/Verilog has been used for 30 years and in my opinion will continue to be used for many mores, Python's language structure just doesn't have what's needed to the hardware domain. I see myself wasting a lot of time having to teach our old hardware guys Python and how to think in terms of RTL with a new Language. That's why i didn't try to switch. Remember, most of the engineers working with hardware come from EE background, not CS. They are more familliar with Schematics than C.

DigitalJack 12y ago
For design I agree. For verification, software techniques are often used and systemverilog has a lot of growing up to do.
Igglyboo 12y ago
This is extremely useful for people with CS backgrounds who want to get into CS. My first dive into VHDL was disasterous, I feel like it would have went much better if I had used something like this with a familiar syntax.