3 ms·
The thing is, all the relevant page table data should already be in L1 caches when the page fault handler returns. The TLB miss on iret should not require raw m
by nhaehnle 13y ago
The thing is, all the relevant page table data should already be in L1 caches when the page fault handler returns. The TLB miss on iret should not require raw memory lookups and should be much faster than 300 cycles.
Probably it's more that iret simply has always been slow (hence why the various syscall/sysenter extensions were created).