For history, UVM (the Universal Verification Methodology -- gee that's original) is basically the same as OVM, which was a SystemVerilog port of eRM (aka Specma

For history, UVM (the Universal Verification Methodology -- gee that's original) is basically the same as OVM, which was a SystemVerilog port of eRM (aka Specman). VMM is the SystemVerilog equivalent of RVM (from Vera). I loved working with RVM and VMM, as to me channel-based transaction (and transactor and scoreboard) programming is very natural and simple to understand. And it's the route that newer languages like Go have taken. UVM (and all the predecessors) have gone the route of TLM (transaction-level modeling), which has no explicit channels. So many of the objects talk directly to other objects, which adds unnecessary coupling. However, the big thing that I dislike with UVM is that it is basically Enterprise Java for SystemVerilog. They have made the API's into this cookie-cutter complex enterprise abstraction, where you have to follow the macros and recipes per the book. Everyone must use the built-in macros, and use packages and factories and sequences and agents and virtual components. And your employees start talking in UVM-speak ("oh that's in his UVC"). </rant>