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There's a new CPU architecture in the pipe(should have good silicon within five years, if their projections can be trusted), and it has a very good design aroun
by microcolonel 13y ago
There's a new CPU architecture in the pipe(should have good silicon within five years, if their projections can be trusted), and it has a very good design around system calls, and also in terms of virtual memory.
It has a single 64-bit address space and only protection contexts, and due to the general design of the system it doesn't require any register push(or registers at all, at least in the traditional sense). In addition, it has primitives which would allow programs to call directly into drivers and kernel services without a context switch.
Anyway, I don't mean to sound like an advertisement, and we've yet to see any silicon, so the jury's out.
Aside: Starting process address spaces at 0 is not really a convenience as far as I know(other than offering consistent addresses for jumping to static symbols), it's a way to enable PAE on 32-bit machines so that single contexts(typically processes) can use the whole address space.
- wolf550e 13y agoYou forgot to provide a link: http://millcomputing.com/docs/ http://millcomputing.com/docs/
- sparkie 13y agoThere's an even bigger revolution in CPU design, with Ivan Sutherland's Fleet - which does away with the clock and sequential execution of instructions - instead, the programming model is based on messaging and traffic control - you direct signals to the units in the chip which perform the computations you want, asynchronously by default - if you need synchronicity, you need to program your own models for it. While these probably won't be available in the next 5 years, and probably won't be acknowledged by existing programmers for decades - I think these ideas will take over. http://arc.cecs.pdx.edu/publications http://arc.cecs.pdx.edu/publications https://www.youtube.com/watch?v=jR9pAaQlVRc https://www.youtube.com/watch?v=jR9pAaQlVRc