VHDL has the same problem: signal x, y: std_logic; ... x <= 'X'; ... y <= '0' when x = '0' else '1'; will result in y getting the value '1' in simul

VHDL has the same problem: signal x, y: std_logic; ... x <= 'X'; ... y <= '0' when x = '0' else '1'; will result in y getting the value '1' in simulation, but you don't know what it'll be for synthesis. So if you're unlucky, it'll simulate correctly but fail in hardware. Which is exactly what simulation should protect you from. And even if you assign only '0' and '1', you might get an 'X' from third-party IP cores.