4 ms·
Not only that, but the early ARM architecture was terrible at running unix or other non-single address space OS's. If I remember correctly, the caches were vir
by salem 13y ago
Not only that, but the early ARM architecture was terrible at running unix or other non-single address space OS's.
If I remember correctly, the caches were virtually tagged, even on the StrongARM, making context switching on linux very expensive.
- stormbrew 13y agoTagged TLBs should make multitasking faster, not slower, unless I don't catch your meaning at all. On a non-tagged cache you have to dump the entire thing whenever you change address spaces. With tags you lazily invalidate only the entries that aren't part of the active virtual id.
- cokernel_hacker 13y agoDifferent kind of tagging. salem is referring to how addresses are compared in the cache: http://en.wikipedia.org/wiki/CPU_cache#Virtual_tags_and_vhints http://en.wikipedia.org/wiki/CPU_cache#Virtual_tags_and_vhin... you are referring to ASIDs which are the mechanism by which different address spaces can share space in the TLB at the same time: http://www.helenos.org/doc/design/html.chunked/mm.html#id2535017 http://www.helenos.org/doc/design/html.chunked/mm.html#id253...