A contributing factor is that the Partition-Place-Route (PPR) software, that is necessary to map a design onto the FPGA die, is proprietary and controlled very

A contributing factor is that the Partition-Place-Route (PPR) software, that is necessary to map a design onto the FPGA die, is proprietary and controlled very tightly by the FPGA vendors, as are the specifications of the raw dies and the meaning of each bit in the corresponding bitstream. Consequently, FPGAs don't lend themselves to an uncontrolled explosion of innovation. Compare with GPUs and CPUs where open source compilers are available and anyone can have a crack at innovating, at whatever level they choose. As an example, if you want to dynamically generate programming for a Xilinx FPGA, you need to incorporate Xilinx's binary only PPR program somewhere into the flow. That acts as a ball and chain around the leg of reconfigurable computing, impeding its development and adoption.