3 ms·

"how much better" -- I didn't understand, sorry. Even with 18 years of x86 performance advances, it takes much longer to PAR the large FPGAs now than it did ba

by jangray 13y ago

"how much better" -- I didn't understand, sorry. Even with 18 years of x86 performance advances, it takes much longer to PAR the large FPGAs now than it did back in the day.

1ris 13y ago
I did expect that. But given the old FPGA: Would you have gotten significantly better results if you would have had a i7 back in 1995? I'm not talking about getting it done faster, but getting it better.
aortega 13y ago
I believe the problem here are the Xilinx tools. They basically suck. Latest Quartus from Altera can build a decent sized (about 10000 LUTs) design in about 10 minutes in my I5 M2520 notebook. I'm currently synthesizing a 45nm ARM cortex-M0 design using Cadence Encounter flow. The complete process (RTL compiler+place+route) takes only 5 minutes!
- jangray 13y ago
  I use both vendors' toolsets, have found occasional bugs in both, have my regrets, but all-in-all they are quite comparable, and quite remarkable for what they enable. In both tools most of my design spins take <3 minutes. If you were building an ASIC you'd pay $$$,$$$ for such tools. The economics of FPGAs are such that the tools are either free or $,$$$. Both are reasonable and accessible to an enthusiast/practicing EE, respectively. I am so grateful to Ross Freeman, inventor of FPGAs, and all the engineers that followed in his footsteps, for democratizing access to state of the art high performance digital logic. For $100 or so you can get a 28 nm device filled with 10,000s of LUTs and hundreds of RAM blocks and build whatever you can imagine. Amazing.
  - aortega 13y ago
    Indeed, I always wonder why such a (relatively) exotic and low-volume technology is also very low-cost. 3 minutes is very fast...one of my projects takes about 30 minutes for ~30K Luts on a modern Core I7, I used too many registers. Developing and debugging it is basically torture.

by jangray 13y ago

"how much better" -- I didn't understand, sorry. Even with 18 years of x86 performance advances, it takes much longer to PAR the large FPGAs now than it did back in the day.

1ris 13y ago

I did expect that. But given the old FPGA: Would you have gotten significantly better results if you would have had a i7 back in 1995? I'm not talking about getting it done faster, but getting it better.

aortega 13y ago

I believe the problem here are the Xilinx tools. They basically suck. Latest Quartus from Altera can build a decent sized (about 10000 LUTs) design in about 10 minutes in my I5 M2520 notebook. I'm currently synthesizing a 45nm ARM cortex-M0 design using Cadence Encounter flow. The complete process (RTL compiler+place+route) takes only 5 minutes!

jangray 13y ago
I use both vendors' toolsets, have found occasional bugs in both, have my regrets, but all-in-all they are quite comparable, and quite remarkable for what they enable. In both tools most of my design spins take <3 minutes. If you were building an ASIC you'd pay $$$,$$$ for such tools. The economics of FPGAs are such that the tools are either free or $,$$$. Both are reasonable and accessible to an enthusiast/practicing EE, respectively. I am so grateful to Ross Freeman, inventor of FPGAs, and all the engineers that followed in his footsteps, for democratizing access to state of the art high performance digital logic. For $100 or so you can get a 28 nm device filled with 10,000s of LUTs and hundreds of RAM blocks and build whatever you can imagine. Amazing.
- aortega 13y ago
  Indeed, I always wonder why such a (relatively) exotic and low-volume technology is also very low-cost. 3 minutes is very fast...one of my projects takes about 30 minutes for ~30K Luts on a modern Core I7, I used too many registers. Developing and debugging it is basically torture.