4 ms·

Hi, Jan here. pdq, the last time I built this design, with more fully elaborated processors (control units + multiplier FUs) it took three hours and 16 GB phys

by jangray 13y ago

Hi, Jan here. pdq, the last time I built this design, with more fully elaborated processors (control units + multiplier FUs) it took three hours and 16 GB physical RAM on a Core i7-4960HQ rMBP.

kbenson 13y ago
Do you know if the process parallelizes well? If so, this seems like something that high-end temporary AWS instances could help quite a bit with.
- jangray 13y ago
  With the Xilinx ISE toolset I am currently using (which Xilinx is deprecating in favor of the new Vivado toolset) it parallelizes/multithreads poorly. I understand that the place and route algorithm is based upon simulated annealing, in which you make small random perturbations to the current layout configuration, measure whether it is better or worse, and sometimes retain the new configuration, and sometimes roll back. This gradually evolves the system to a configuration which maximizes some objective function, avoiding getting stuck in a local maximum. It has traditionally been a challenge to parallelize this sequential algorithm through design partitioning because of placement and routing interactions between the partitions. In some flows you can do a coarse floorplan of your design and route the submodules separately and then stitch them together. I imagine this is how the very largest devices are implemented in manageable design iteration times. I don't usually worry about that, though. Since my design is just so many replicated tiles, I tend to do design iterations of 4- or 16-processor elements to test the impact on clock period / timing slack. That usually takes 2-3 minutes per design spin. Only once in a while do I place and route the whole chip to confirm some change doesn't impact timing closure.
  - deleted 13y ago
    [deleted]
1ris 13y ago
Considering that the synthesis is a PN-hard problem (I think so?), how much better is your 1995 design in a 1995 FPGA synthesized with a 2014 CPU compared with a 1995 CPU? Is there a huge difference?
- jangray 13y ago
  "how much better" -- I didn't understand, sorry. Even with 18 years of x86 performance advances, it takes much longer to PAR the large FPGAs now than it did back in the day.
  - 1ris 13y ago
    I did expect that. But given the old FPGA: Would you have gotten significantly better results if you would have had a i7 back in 1995? I'm not talking about getting it done faster, but getting it better.
  - aortega 13y ago
    I believe the problem here are the Xilinx tools. They basically suck. Latest Quartus from Altera can build a decent sized (about 10000 LUTs) design in about 10 minutes in my I5 M2520 notebook. I'm currently synthesizing a 45nm ARM cortex-M0 design using Cadence Encounter flow. The complete process (RTL compiler+place+route) takes only 5 minutes!
    - jangray 13y ago
      I use both vendors' toolsets, have found occasional bugs in both, have my regrets, but all-in-all they are quite comparable, and quite remarkable for what they enable. In both tools most of my design spins take <3 minutes. If you were building an ASIC you'd pay $$$,$$$ for such tools. The economics of FPGAs are such that the tools are either free or $,$$$. Both are reasonable and accessible to an enthusiast/practicing EE, respectively. I am so grateful to Ross Freeman, inventor of FPGAs, and all the engineers that followed in his footsteps, for democratizing access to state of the art high performance digital logic. For $100 or so you can get a 28 nm device filled with 10,000s of LUTs and hundreds of RAM blocks and build whatever you can imagine. Amazing.

by jangray 13y ago

Hi, Jan here. pdq, the last time I built this design, with more fully elaborated processors (control units + multiplier FUs) it took three hours and 16 GB physical RAM on a Core i7-4960HQ rMBP.

kbenson 13y ago

Do you know if the process parallelizes well? If so, this seems like something that high-end temporary AWS instances could help quite a bit with.

jangray 13y ago
With the Xilinx ISE toolset I am currently using (which Xilinx is deprecating in favor of the new Vivado toolset) it parallelizes/multithreads poorly. I understand that the place and route algorithm is based upon simulated annealing, in which you make small random perturbations to the current layout configuration, measure whether it is better or worse, and sometimes retain the new configuration, and sometimes roll back. This gradually evolves the system to a configuration which maximizes some objective function, avoiding getting stuck in a local maximum. It has traditionally been a challenge to parallelize this sequential algorithm through design partitioning because of placement and routing interactions between the partitions. In some flows you can do a coarse floorplan of your design and route the submodules separately and then stitch them together. I imagine this is how the very largest devices are implemented in manageable design iteration times. I don't usually worry about that, though. Since my design is just so many replicated tiles, I tend to do design iterations of 4- or 16-processor elements to test the impact on clock period / timing slack. That usually takes 2-3 minutes per design spin. Only once in a while do I place and route the whole chip to confirm some change doesn't impact timing closure.
- deleted 13y ago
  [deleted]

1ris 13y ago

Considering that the synthesis is a PN-hard problem (I think so?), how much better is your 1995 design in a 1995 FPGA synthesized with a 2014 CPU compared with a 1995 CPU? Is there a huge difference?

jangray 13y ago
"how much better" -- I didn't understand, sorry. Even with 18 years of x86 performance advances, it takes much longer to PAR the large FPGAs now than it did back in the day.
- 1ris 13y ago
  I did expect that. But given the old FPGA: Would you have gotten significantly better results if you would have had a i7 back in 1995? I'm not talking about getting it done faster, but getting it better.
- aortega 13y ago
  I believe the problem here are the Xilinx tools. They basically suck. Latest Quartus from Altera can build a decent sized (about 10000 LUTs) design in about 10 minutes in my I5 M2520 notebook. I'm currently synthesizing a 45nm ARM cortex-M0 design using Cadence Encounter flow. The complete process (RTL compiler+place+route) takes only 5 minutes!
  - jangray 13y ago
    I use both vendors' toolsets, have found occasional bugs in both, have my regrets, but all-in-all they are quite comparable, and quite remarkable for what they enable. In both tools most of my design spins take <3 minutes. If you were building an ASIC you'd pay $$$,$$$ for such tools. The economics of FPGAs are such that the tools are either free or $,$$$. Both are reasonable and accessible to an enthusiast/practicing EE, respectively. I am so grateful to Ross Freeman, inventor of FPGAs, and all the engineers that followed in his footsteps, for democratizing access to state of the art high performance digital logic. For $100 or so you can get a 28 nm device filled with 10,000s of LUTs and hundreds of RAM blocks and build whatever you can imagine. Amazing.