4 ms·

Fab tech has improved at an astonishing rate. The Willamette core (Pentium 4) from 2000 fit 42 million transistors in 217mm². Eight years later, Silverthorne (A

by ggreer 13y ago

Fab tech has improved at an astonishing rate. The Willamette core (Pentium 4) from 2000 fit 42 million transistors in 217mm². Eight years later, Silverthorne (Atom) fit two cores and 47 million transistors in 25mm². That's nine Atom CPUs in the same space as one Pentium 4. Today's quad-core Haswell is made of 1.4 billion transistors crammed into 177mm². That's almost 8 million transistors per square millimeter.

anigbrowl 13y ago
It seems like we're going to run into the limits of that by the end of the decade or soon after though. I've made quite a few submissions about this but nobody ever seems to read them :) I really wonder whether we are making advances with parallelism and other technologies fast enough to offset the oncoming barriers to shrinkage and speed. My naive best guess is that when CPUs stop getting much faster the next wave of innovation will be on bus speeds. But I'm not a chip guy so perhaps my view of the problem is overblown, but I'm very interested in learning more about this from others.
- hershel 13y ago
  Yes moore's law is in deep troubles, but there are few paths for innovation in that area: bus speeds, imprecise but faster and lower power computation(which works for some things), much more efficient ways to build on chip memory(which takes 50% of chip area), 3d manufacturing techniques to decrease cost, ,affordable ways to make customizable microprocessors and moving from silicon to other materials to achieve much lower power consumption. So on average we might be able to see 50x improvement in the next 30 years (according to a darpa manager).
- zhemao 13y ago
  > when CPUs stop getting much faster If by faster you mean clock speed, they haven't been getting faster for a while now. Memory and IO speeds do lag behind, but we have caching to solve the former and SSDs to solve the latter. One pressing issue now is getting the power consumption down. This is especially important for laptops and mobile phones. FPGAs are pretty good at using less power, but you have to sacrifice a lot of performance and programmability.
  - anigbrowl 13y ago
    Ah sorry, I meant in terms of execution speed not clock, and was thinking mainly of shrinking die sizes > more transistors > more operations per cycle. I apologize for the vagueness.

by ggreer 13y ago

anigbrowl 13y ago

It seems like we're going to run into the limits of that by the end of the decade or soon after though. I've made quite a few submissions about this but nobody ever seems to read them :) I really wonder whether we are making advances with parallelism and other technologies fast enough to offset the oncoming barriers to shrinkage and speed. My naive best guess is that when CPUs stop getting much faster the next wave of innovation will be on bus speeds. But I'm not a chip guy so perhaps my view of the problem is overblown, but I'm very interested in learning more about this from others.

hershel 13y ago
Yes moore's law is in deep troubles, but there are few paths for innovation in that area: bus speeds, imprecise but faster and lower power computation(which works for some things), much more efficient ways to build on chip memory(which takes 50% of chip area), 3d manufacturing techniques to decrease cost, ,affordable ways to make customizable microprocessors and moving from silicon to other materials to achieve much lower power consumption. So on average we might be able to see 50x improvement in the next 30 years (according to a darpa manager).
zhemao 13y ago
> when CPUs stop getting much faster If by faster you mean clock speed, they haven't been getting faster for a while now. Memory and IO speeds do lag behind, but we have caching to solve the former and SSDs to solve the latter. One pressing issue now is getting the power consumption down. This is especially important for laptops and mobile phones. FPGAs are pretty good at using less power, but you have to sacrifice a lot of performance and programmability.
- anigbrowl 13y ago
  Ah sorry, I meant in terms of execution speed not clock, and was thinking mainly of shrinking die sizes > more transistors > more operations per cycle. I apologize for the vagueness.