#1) Mill cache is relatively conventional (except with 9-bit bytes). Everybody uses the EDA tools to create caches, so everybody will get similar power numbers.

#1) Mill cache is relatively conventional (except with 9-bit bytes). Everybody uses the EDA tools to create caches, so everybody will get similar power numbers. However, there's a lot more to the hierarchy power budget than the caches: read buffers, write buffers, pin drivers, etc. The Mill has neither read nor write buffering, and backless lines don't drive pins. We won't have good numbers until we have gate-level sims of the hierarchy, so for now all there is to go on is skill and expertise. We're not worried; YMMV. #2) The bypass is similar for the FU-to-FU paths, but an OOO has to also feed from the renames that the Mill doesn't have. #3) The OS port is a largely solved problem: we expect to use the L4 microkernel as a base and the existing L4-based Linux etc. implementations on that. https://en.wikipedia.org/wiki/L4_microkernel_family https://en.wikipedia.org/wiki/L4_microkernel_family. Porting L4 to the Mill is pretty easy; we designed it that way :-)