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I use Altium every day for board layouts and schematics. It is a fantastic software package - worth every penny, and easily affordable to small-to-medium busin

by swamp40 13y ago

I use Altium every day for board layouts and schematics. It is a fantastic software package - worth every penny, and easily affordable to small-to-medium businesses. I'll bet they have 100+ programmers constantly improving their product. Every version is more powerful and easier to use. No way for a small startup to compete with that without charging a similar amount. And even then, Altium has a 20 year head-start.

cottonseed 13y ago
Well, I'm not thinking about a startup, but open source projects. You could have said the same thing about any of the commercial unix vendors in the early 90s -- they had a 15 year head start, hundreds of programmers, etc. And look where we are now. What could things look like in 20 years?
- sliverstorm 13y ago
  One of the big challenges as I see it with EDA tools- the target moves quickly. In silicon development, for example, suddenly all your customers want double-patterning support in your tools as they move to today's tiny process nodes. [0] Or, perhaps, your customers now need layer-aware optimization, again for recent processes. [1] You have to accommodate this very quickly. An ASIC program runs for a year or three, so your EDA tools need to add & mature these new features in a very short timeframe. (Well, the feature doesn't have to be mature right away, but it does have to work) This means it's a hard environment to compete in. You could develop an open-source offering to compete, but without very significant resources your tools will always be missing support for modern processes. [0]: http://www.techdesignforums.com/practice/guides/double-patterning/ http://www.techdesignforums.com/practice/guides/double-patte... [1]: http://www.eetimes.com/document.asp?doc_id=1279842 http://www.eetimes.com/document.asp?doc_id=1279842 On a completely separate angle, compiling & optimization is basically the biggest Packing Problem you've ever faced, with several dimensions of "packing". You need some very smart people to hope to produce good results. But I've written enough for now.
  - cottonseed 13y ago
    I agree that's true for chip design tools, but I was mostly thinking board-level design and above. Although I think there is opportunity in chip design for higher level tools not tied to chip design. To things spring to mind. After the Pentium fdiv bug, Intel hired the author of the HOL Light theorem prover. He formalized the FPU of a later chip. I'm also thinking of high-level synthesis tools like Arvind's Bluespec.

by swamp40 13y ago

cottonseed 13y ago

Well, I'm not thinking about a startup, but open source projects. You could have said the same thing about any of the commercial unix vendors in the early 90s -- they had a 15 year head start, hundreds of programmers, etc. And look where we are now. What could things look like in 20 years?

sliverstorm 13y ago
One of the big challenges as I see it with EDA tools- the target moves quickly. In silicon development, for example, suddenly all your customers want double-patterning support in your tools as they move to today's tiny process nodes. [0] Or, perhaps, your customers now need layer-aware optimization, again for recent processes. [1] You have to accommodate this very quickly. An ASIC program runs for a year or three, so your EDA tools need to add & mature these new features in a very short timeframe. (Well, the feature doesn't have to be mature right away, but it does have to work) This means it's a hard environment to compete in. You could develop an open-source offering to compete, but without very significant resources your tools will always be missing support for modern processes. [0]: http://www.techdesignforums.com/practice/guides/double-patterning/ http://www.techdesignforums.com/practice/guides/double-patte... [1]: http://www.eetimes.com/document.asp?doc_id=1279842 http://www.eetimes.com/document.asp?doc_id=1279842 On a completely separate angle, compiling & optimization is basically the biggest Packing Problem you've ever faced, with several dimensions of "packing". You need some very smart people to hope to produce good results. But I've written enough for now.
- cottonseed 13y ago
  I agree that's true for chip design tools, but I was mostly thinking board-level design and above. Although I think there is opportunity in chip design for higher level tools not tied to chip design. To things spring to mind. After the Pentium fdiv bug, Intel hired the author of the HOL Light theorem prover. He formalized the FPU of a later chip. I'm also thinking of high-level synthesis tools like Arvind's Bluespec.