3 ms·
There could be an ASIC for that. There's a new memory interface that works at 10 TB/sec with 16GB memory[1].Currently there's no cpu/gpu architecture in plannin
by hershel 13y ago
There could be an ASIC for that. There's a new memory interface that works at 10 TB/sec with 16GB memory[1].Currently there's no cpu/gpu architecture in planning that's even close to needing that memory bandwidth, and the manufacturing is expensive.
All this means this tech won't fit decentralization well.
[1]http://www.eetimes.com/author.asp?section_id=36&doc_id=1320951 http://www.eetimes.com/author.asp?section_id=36&doc_id=13209...
- deleted 13y ago[deleted]
- Retric 13y agoBandwidth and latency are two seperate concepts, that 10TB bandwidth is probably around 100MB/second if you need truly random access to individual bytes of 16GB of ram and need to read each byte to find out which byte you need next. It's a speed of light issue where the round trip time back and forth to the individual RAM chips adds an inherent delay so RAM designers don't really focious on reducing latency as your stuck with a farly high latency anyway so bandwidth is generally more useful.