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I don't know the details for ARM, but generally, microcontroller type CPUs don't do any reordering, so no need to prevent it with barriers. And if you do use vo
by zAy0LfpBZLC8mAC 13y ago
I don't know the details for ARM, but generally, microcontroller type CPUs don't do any reordering, so no need to prevent it with barriers. And if you do use volatile correctly (and the compiler is not broken), you don't need compiler barriers either. You also might not need any CPU barriers when the cache controller is configured to treat certain regions of the address space as uncacheable (which might be used for MMIO regions).
- acqq 13y agoWell, with the sufficiently primitive CPU and C compiler even volatile is not needed.
- zAy0LfpBZLC8mAC 13y agoSure - except that "primitive" CPUs are still widely used, while I'd think that non-optimizing C compilers are the exception.
- mansr 13y agoModern high-performance ARM cores such as the Cortex-A15 do plenty of reordering. Even when using strongly ordered memory mappings, you still need barriers to prevent reordering between normal and strongly ordered accesses. No amount of volatile will help with this.
- zAy0LfpBZLC8mAC 13y agoThe parent's parent was talking about microcontroller class ARMs, though. Also, you don't necessarily have to order "normal" with regards to strongly ordered accesses. If it's only about ordering accesses to MMIO, it doesn't matter when some arithmetic result gets stored to RAM relative to those accesses, all that matters is that the hardware sees the register reads and writes in the right order. Ordering only matters for stuff that is shared in some way, for private data, the illusion of naive serial execution is guaranteed anyhow.
- mansr 13y agoA common scenario is filling a data buffer in normal memory (cached or non-cached doesn't matter on ARM) before initiating a DMA operation by writing to a device register. In this situation, a barrier is required to prevent any of the normal writes being reordered around the DMA initiation which would then see stale data in the buffer. Discussions about barriers (or volatile) are only meaningful in the context of related accesses, so explicitly mentioning this isn't really necessary.
- zAy0LfpBZLC8mAC 13y agoI don't really get what you are trying to say. Sure, there are cases where you need barriers, both the CPU and the compiler kind, nobody denied that. Still, in low-end stuff, PIO and cache-free in-order execution still are well and alive, and volatile can be perfectly sufficient under such circumstances.
- mansr 13y agoThe ARMv7-M architecture (which the popular Cortex-M series microcontrollers implement) allows reordering as I described. Even if a Cortex-M3 probably doesn't ever do it, nobody is making any promises. If a particular behaviour is not documented, it is wrong to rely on it.
- colin_mccabe 13y agoI don't really get what you are trying to say. volatile is an antipattern. Don't use it. Don't encourage other people to use it. It is not a thing which should be used, by you. To use it would be wrong, because not using it is correct. Use atomic instructions.