4 ms·
This article is spectacularly good. I wish I had this available when I started doing assembly-level optimizations on x86 chips. This knowledge used to be much m
by jwr 13y ago
This article is spectacularly good. I wish I had this available when I started doing assembly-level optimizations on x86 chips. This knowledge used to be much more fragmented and difficult to learn.
VLIW could indeed be left out: you are not likely to encounter a VLIW chip, and if you do, it will come with an (excellent) compiler that will do most of the hard work for you.
A good followup article would be a tutorial on how to lay out your structures/arrays in memory given your access patterns and cache architecture.
- dfox 13y agoIn my experience, when you encounter VLIW cores, there is almost no tooling for it as they tend be application specific DSP-ish cores. In that case hand optimized assembly is the way to go as there is no budget to produce optimizing compiler of anything.
- jwr 13y agoMy experience was with Texas Instruments C6000 DSPs. The compiler is excellent and if you use it well, you rarely have to resort to assembly. Even then, you normally write linear assembly, not parallel assembly, letting the assembler take care of the rest.