You found the problem, congratulations. Both code samples are the recommended way to generate an asynchronous set/reset flip-flop for an ASIC flow (minus my ba

You found the problem, congratulations. Both code samples are the recommended way to generate an asynchronous set/reset flip-flop for an ASIC flow (minus my bad memory about details of the VHDL syntax). For years, Design Compiler has forced ASIC designers to describe level sensitive pins (set or reset) as if they were edge triggered, which is correct in most cases, except the case you outlined. So those two codes generate the exact same logic after synthesis, but you can have mismatches with simulation. And there is actually nothing you could do about it to fix the Verilog since you need your synthesis tool to understand your intent. The correction you propose is the correct one from a simulation viewpoint, but DC would reject it. Luckily, the case where you assert both set and reset on a flop to then deassert reset are fairly rare... I was on the IEEE standardization committee for VHDL synthesis: since then I know why [some] standards don't make sense.