3 ms·

I'm sure there's an excellent reason, but the first thing I think whenever I see something like this is .. why doesn't intel (or whoeever) load up the CPUs with

by sho 17y ago

I'm sure there's an excellent reason, but the first thing I think whenever I see something like this is .. why doesn't intel (or whoeever) load up the CPUs with more L1 and L2 cache? Are there really diminishing returns so quickly after 6MB, or would the size increase make the expense not worth it? And is it impossible to make it modular and expandable? It would be interesting to see some account of the cache size / die size cost / performance trade-offs.

wmf 17y ago
It's commonly accepted that the cost of a chip is super-linear in its area but performance improves sub-linearly with cache size, so there is definitely a point of diminishing returns. Processor vendors analyze cost/performance tradeoffs in detail, but they generally don't publish anything.
- sho 17y ago
  Yeah, that's what I figured. Be nice to see some numbers though. Not like I have a hope in hell of getting anything I write even into 6MB .. sigh.
ajross 17y ago
They do: http://images.google.com/images?hl=en&q=nehalem+die http://images.google.com/images?hl=en&q=nehalem+die Nehalem is about 70% cache. Most of it is the shared L3 between cores. There are physical limits to how large a cache can be and still run synchronously. The L1 is still tiny (64k, split between instructions data), and it's really not feasible to make it larger without affecting clock speed. But if you drop just a little bit and pay a latency cost, you can stick a 256k unified cache on each core. Then they all talk to the 3M shared "uncore" cache. But to first approximation, a modern "CPU" is entirely SRAM.
paddy_m 17y ago
What is the difference between L1 and L2 cache? I know that L2 caches are generally larger. Is it more expensive so far as silicon real estate, to make 1k of L1 cache vs 1k of L2 cache? The last I heard, both L1 and L2 cache were sram based which used 6 transitors per bit. I also remember that ram takes either 2 or 4 transitors per bit + a capacitor. If L1 and L2 cache take the same number of number of transistors per bit, what is the difference?
- wmf 17y ago
  Yes, L1 and L2 are made from the same 6T SRAM. The access time of a cache is proportional to something like the square root of the capacity since signals may have to travel to the opposite side of the cache and back. Because of locality, it's better to have something like a 3-cycle L1 and a 15-cycle L2 than a single 12-cycle cache.

by sho 17y ago

wmf 17y ago

It's commonly accepted that the cost of a chip is super-linear in its area but performance improves sub-linearly with cache size, so there is definitely a point of diminishing returns. Processor vendors analyze cost/performance tradeoffs in detail, but they generally don't publish anything.

sho 17y ago
Yeah, that's what I figured. Be nice to see some numbers though. Not like I have a hope in hell of getting anything I write even into 6MB .. sigh.

ajross 17y ago

They do: http://images.google.com/images?hl=en&q=nehalem+die http://images.google.com/images?hl=en&q=nehalem+die Nehalem is about 70% cache. Most of it is the shared L3 between cores. There are physical limits to how large a cache can be and still run synchronously. The L1 is still tiny (64k, split between instructions data), and it's really not feasible to make it larger without affecting clock speed. But if you drop just a little bit and pay a latency cost, you can stick a 256k unified cache on each core. Then they all talk to the 3M shared "uncore" cache. But to first approximation, a modern "CPU" is entirely SRAM.

paddy_m 17y ago

What is the difference between L1 and L2 cache? I know that L2 caches are generally larger. Is it more expensive so far as silicon real estate, to make 1k of L1 cache vs 1k of L2 cache? The last I heard, both L1 and L2 cache were sram based which used 6 transitors per bit. I also remember that ram takes either 2 or 4 transitors per bit + a capacitor. If L1 and L2 cache take the same number of number of transistors per bit, what is the difference?

wmf 17y ago
Yes, L1 and L2 are made from the same 6T SRAM. The access time of a cache is proportional to something like the square root of the capacity since signals may have to travel to the opposite side of the cache and back. Because of locality, it's better to have something like a 3-cycle L1 and a 15-cycle L2 than a single 12-cycle cache.