I'll bite the bullet: Funnily enough, I think this sort of design fails to account for Moore's law (different Moore, you see). The principle here is to drop ma

I'll bite the bullet: Funnily enough, I think this sort of design fails to account for Moore's law (different Moore, you see). The principle here is to drop many of the principles that make modern processors fast: pipelines, caches, large register files, rich instruction sets (e.g. different instructions for different data sizes, DSP-style instructions, SIMD, etc). You end up with a really simple core, easy to implement, cheap in terms of die area. This might work well for certain applications (maybe as a power efficient microcontroller), but you're left with two major issues: 1) you have no other way to increase its performance apart from increasing the clock frequency - we know that pretty much stalled; and 2) you'll discover at some point that while hitting the cache is expensive in terms of energy, it's still better than hitting the off-chip RAM, and since you always have to go to the RAM... Apart from that, DRAM bandwidth has sort of kept up with processor frequency, but latency hasn't. At this point, you might think that this design would work well in a manycore system. Well, the problem with that is that we haven't quite figured out the algorithms and software for many-core systems. Pretty much anything apart from data-parallel problems scales worse than linearly on manycore. That being said, there's one feature that I quite like: having an exposed separate return stack could improve the performance of virtualisation (dynamic translation), JIT engines and so on. Modern architectures have an internal RS used for branch prediction, but it's usually not architecturally exposed. tl;dr: Moore's law led to fast RISC/CISC, MISC can only scale horizontally (many-core), which limits its usefulness.