3 ms·
Speeding FPGAs up to 1.5Ghz by getting rid of the global clock
- papaf 17y agoIt would be cool if this worked with noticable speedup. I am skeptical though because people have been looking at async chips for a long time but there hasn't been a revolution. The disadvantage of async chips is that subsystems become more complex (and slower) as they use latches instead of straight logic gates.