Between writing and formally verifying HDL, logic synthesis (often using third-party or vendor-provided blocks or soft IP, mind you), behavioral and logic simul

Between writing and formally verifying HDL, logic synthesis (often using third-party or vendor-provided blocks or soft IP, mind you), behavioral and logic simulation (software!), layout, MDP, and building test harnesses that actually test the final hardware, I would actually trust a lower-level language compiled using a well-known compiler and running on a small RTOS on a proven CPU more than I'd trust a new design synthesized into FPGA or especially ASIC form.