Im an electrical engineer with 10 years FPGA and circuit design experience which includes teaching a few new-hires how to do hardware development. The key to g

Im an electrical engineer with 10 years FPGA and circuit design experience which includes teaching a few new-hires how to do hardware development. The key to getting a synthesizer to produce a good circuit from any HDL, especially Verilog, is to understand that there is a synthesizeable subset of the language that should be used to describe the RTL (Register Transer Level) of abstraction. The rest of the language's constructs should be limited to simulation only. Here are a couple of quickly googled sources just to cement the point: http://users.ece.cmu.edu/~jhoe/course/ece447/handouts/LV.pdf http://users.ece.cmu.edu/~jhoe/course/ece447/handouts/LV.pdf http://en.wikipedia.org/wiki/VHDL#Synthesizable_constructs_and_VHDL_templates http://en.wikipedia.org/wiki/VHDL#Synthesizable_constructs_a... The synthesizable subset tends to be a very small number of constructs and once you know and understand them you will be one big step closer to much "easier" hardware development. One should strive to understand RTL as a level of abstraction first though IMHO. I have some thoughts on how best to do that if anyone cares I can continue.