Hardware engineer here, answering the blogger: this code is bad news to me: only constants should be on the right side of the assigns in the reset branch, so th

Hardware engineer here, answering the blogger: this code is bad news to me: only constants should be on the right side of the assigns in the reset branch, so the tools should definitely be complaining. Second, on the combinatorial always block. The rule is simple: unless you want latches to be inferred (which is usually never), use "always @(*)" so that the block is executed on changes to any of the right-hand-side signals. This is less tedious and error prone than listing each of the signals (there could be 100s in a large block). VHDL and Verilog are semantically equivalent, so no particular advantage to either one (I prefer Verilog since its syntax is a bit more C like, and a bit less Ada like). I've seen many attempts over the years to make languages which make it easier for programmers to do chip designs, but they've all failed. (Most recent is openCL, but it's not a complete chip design language). The coder really has to have some idea about the physical correspondence between his code and the chip. For example, you can easily fill even the largest FPGA with just a few lines of Verilog: reg [10000000:0] foo; always @(posedge clk) foo <= foo + 1'd1; (10 M flops.. will not fit).