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Shameless promotion: MyHDL(Python library for hardware description) is well designed and feature rich. I recently pushed support for using class instances to gr
by jck 13y ago
Shameless promotion: MyHDL(Python library for hardware description) is well designed and feature rich. I recently pushed support for using class instances to group together signals/ports. So, class instances can be used as Interfaces. This is really cool since Verilog/VHDL don't support this feature natively but MyHDLs conversion creates synthesizable Verilog/VHDL. Although system verilog has Interfaces, I'm not sure if synthesis tools support it(Quartus doesn't)
Also, I'm currently working on uhdl, which simplifies a lot of things about using MyHDL such as CoSimulating with icarus/modelsim.
links:
http://myhdl.org http://myhdl.org
https://github.com/jck/uhdl https://github.com/jck/uhdl
- ginty 13y agoThanks for sharing, looks interesting. Would you mind commenting on the development model for something like this? Do you do this on your own time or company sponsored time? I mentioned in another comment that I have a framework along similar lines that has been developed within the company that I work for (Freescale Semiconductor) and I am looking for examples of other semiconductor-related open source projects that I can cite in discussions with management about releasing it. If this was something that you developed within a company could you comment on how you went about open sourcing it?
- jck 13y agooops, I guess that comment insinuates that I'm the creator of MyHDL. The creator of MyHDL is actually Jan Decaluwe(Sigasi, Easics). I just implemented the interfaces feature and develop uhdl. Rgen looks really interesting. I hope you do manage to get it opensourced so that I can play with it!