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I'd also be interested in open-source projects in either VHDL/Verilog, the best i've seen is opencores but it seems to have died a little.
by dchester195 13y ago
I'd also be interested in open-source projects in either VHDL/Verilog, the best i've seen is opencores but it seems to have died a little.
- dominicgs 13y agoI'm not sure what sort of project you're interested in, but we're currently building open source network taps using PHY ICs and an FPGA. As part of the project a USB 3.0 core is being developed to move captured data to a host system. https://github.com/mossmann/daisho https://github.com/mossmann/daisho
- deleted 13y ago[deleted]