It'd probably be easier to design an ultra-long delay line ASIC that internally maintains a state for a certain count of clock cycles, and spits it out after a

It'd probably be easier to design an ultra-long delay line ASIC that internally maintains a state for a certain count of clock cycles, and spits it out after a while. It might still be possible to do a cryogenic attack, but that wouldn't be very easy to do. Or maybe some sort of superconductor/magnetic state device.