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Any ARM experts around? The sagacity of the move to 64-bit is explained in terms of getting rid of cruft, and via analogy to a similar move by Intel on the x86

Any ARM experts around? The sagacity of the move to 64-bit is explained in terms of getting rid of cruft, and via analogy to a similar move by Intel on the x86 line. But I thought that the largest boost to that line comes from the many additional registers available under 64 bit mode. In ARM, with its RISC architecture, there are already a nice number of registers, so I'm wondering where the true advantage lies -- especially an environment of strongly constrained memory.

deleted 13y ago
[deleted]
pja 13y ago
Yes, the biggest boost to x86 performance in the move to 64 bit came mostly because they doubled the number of regsiters available to what was previously a very register poor ISA. The ARM ISA has different legacy issues: the design makes it much more expensive than it otherwise would be to pipeline the CPU in order to get decent performance. The ISA was designed for an in-order CPU: at the time pipelining was something that mainframe / workstation class CPUs did. (ARM was designed in the very early 80s; Intel released a pipelined CPU in 1989 - the 486, and then only for simple instructions.) For instance, every ARM32 assembly instruction has a bunch of condition codes which determine whether to execute the instruction depending on the state of the status bits in the program counter. You can also determine whether a given instruction will set the relevant status bits in the processor. This means you can do nice things like encode an if (R2 < 0) then (Add 1 to R3) else (Add 1 to R4) in just three instructions: one for the test, an instruction if the relevant flag is set & a second instruction to run if it's not set. No branches! You can also branch on any or all of the condition flags. This makes for very compact code. The trouble is that it's hell to pipeline because you have to keep track of all the possible states of the status bits and follow all the possible branch paths that result, whilst keeping track of all the dependencies. They've also done things like simplify the exception handling so that the CPU needs fewer shadow registers, which again reduces power requirements.
- pja 13y ago
  RealWorldTech has a good article here: http://www.realworldtech.com/arm64/ http://www.realworldtech.com/arm64/ if anyone wants to do a slightly deeper dive into the ARM64 ISA.
tompudding 13y ago
It's worth noting that there are double the number of general purpose registers concurrently available in A64 (30 up from 15). I have no idea what effect that has on performance, but it's not the case that there is no improvement in that regard.
- masklinn 13y ago
  > It's worth noting that there are double the number of general purpose registers Yeah same as x86 -> x86-64, but x86 was really starved in general purpose registers with only 6 GPR. Even in ARMv7, ARM had 2.5 times the number of registers of x86 making register pressure a much lower issue. This means the performance gains from lowered register pressure are going to be significantly lower on ARM, as register pressure was much, much lower in the first place.
rsynnott 13y ago
From the data presented, it looks like most of the performance gains are actually from improvements in Apple's micro architecture (they show up even using ARMv7 code).

deleted 13y ago

[deleted]

pja 13y ago

Yes, the biggest boost to x86 performance in the move to 64 bit came mostly because they doubled the number of regsiters available to what was previously a very register poor ISA. The ARM ISA has different legacy issues: the design makes it much more expensive than it otherwise would be to pipeline the CPU in order to get decent performance. The ISA was designed for an in-order CPU: at the time pipelining was something that mainframe / workstation class CPUs did. (ARM was designed in the very early 80s; Intel released a pipelined CPU in 1989 - the 486, and then only for simple instructions.) For instance, every ARM32 assembly instruction has a bunch of condition codes which determine whether to execute the instruction depending on the state of the status bits in the program counter. You can also determine whether a given instruction will set the relevant status bits in the processor. This means you can do nice things like encode an if (R2 < 0) then (Add 1 to R3) else (Add 1 to R4) in just three instructions: one for the test, an instruction if the relevant flag is set & a second instruction to run if it's not set. No branches! You can also branch on any or all of the condition flags. This makes for very compact code. The trouble is that it's hell to pipeline because you have to keep track of all the possible states of the status bits and follow all the possible branch paths that result, whilst keeping track of all the dependencies. They've also done things like simplify the exception handling so that the CPU needs fewer shadow registers, which again reduces power requirements.

pja 13y ago
RealWorldTech has a good article here: http://www.realworldtech.com/arm64/ http://www.realworldtech.com/arm64/ if anyone wants to do a slightly deeper dive into the ARM64 ISA.

tompudding 13y ago

It's worth noting that there are double the number of general purpose registers concurrently available in A64 (30 up from 15). I have no idea what effect that has on performance, but it's not the case that there is no improvement in that regard.

masklinn 13y ago
> It's worth noting that there are double the number of general purpose registers Yeah same as x86 -> x86-64, but x86 was really starved in general purpose registers with only 6 GPR. Even in ARMv7, ARM had 2.5 times the number of registers of x86 making register pressure a much lower issue. This means the performance gains from lowered register pressure are going to be significantly lower on ARM, as register pressure was much, much lower in the first place.

rsynnott 13y ago

From the data presented, it looks like most of the performance gains are actually from improvements in Apple's micro architecture (they show up even using ARMv7 code).