Any modern ASIC being built would be tested using Automatic Test Pattern Generation. This involves connecting all the registers in the chip into a chain and fe

Any modern ASIC being built would be tested using Automatic Test Pattern Generation. This involves connecting all the registers in the chip into a chain and feeding patterns in and out of the chains and stimulating the logic between registers in a defined manner. These tests will at one level be looking for Stuck and 0 and Stuck at 1 faults and typically nobody would tape out a chip without >99% coverage. It would be very difficult to fiddle with individual gates as the author describes without this being detected with an ATPG test.