3 ms·

Spent the last 2 years doing high-speed comm designs on FPGAs. (I don't know if 5 Gbps currently count as high speed though). The tools are quite mature and wil

by aortega 13y ago

Spent the last 2 years doing high-speed comm designs on FPGAs. (I don't know if 5 Gbps currently count as high speed though). The tools are quite mature and will mostly prevent you from doing stupid things. Somewhere here I saw a comment saying that you must time your design taking in account the logic delay or will get weird errors, but that's impossible. The tool chain (both quartus and Xilinx ISE) will report the max clock speed with a big bold red font if you try to go faster. There's a step in every design flow called DRC (Design rule-checker), basically a bunch of warnings if you do dumb things with anything including the high-speed transcievers. You must pay attention to the warnings. Neverd did any ASIC but I know they have about 10X the testing and simulation that FPGA have. I would believe you don't get random errors if you follow the standard design flow and tests.

beambot 13y ago
Hrm... I've definitely included double-buffering on some signals to prevent metastability between clock domains. I'm not sure if ISE catches all such errors, but it was a low-resource sanity check that made me feel a lot better.
sliverstorm 13y ago
I would believe you don't get random errors if you follow the standard design flow and tests In ASIC, or FPGA? With FPGA, you're probably right. With ASIC, it will depend on your goals. For example, I'm not aware of an industry standard methodology for accounting for the timing impact of localized supply droop. I believe that's something you have to cook up yourself.
MichaelSalib 13y ago
Neverd did any ASIC but I know they have about 10X the testing and simulation that FPGA have. My spouse designs CPUs for a major CPU manufacturer (you've used them). She is responsible for physical design for one tile (there are many tiles, each of which has other physical designers). Her single tile, by itself, is substantially larger than almost all ASIC designs in the world today. At that scale, most of the standard FPGA design tools don't even work. Designing in that space is substantially different than FPGA or even ASIC design.
- sliverstorm 13y ago
  The third type after FPGA and ASIC, sometimes called "full custom". Related to ASIC, but distinct. http://en.wikipedia.org/wiki/Full_custom http://en.wikipedia.org/wiki/Full_custom

by aortega 13y ago

beambot 13y ago

Hrm... I've definitely included double-buffering on some signals to prevent metastability between clock domains. I'm not sure if ISE catches all such errors, but it was a low-resource sanity check that made me feel a lot better.

sliverstorm 13y ago

I would believe you don't get random errors if you follow the standard design flow and tests In ASIC, or FPGA? With FPGA, you're probably right. With ASIC, it will depend on your goals. For example, I'm not aware of an industry standard methodology for accounting for the timing impact of localized supply droop. I believe that's something you have to cook up yourself.

MichaelSalib 13y ago

Neverd did any ASIC but I know they have about 10X the testing and simulation that FPGA have. My spouse designs CPUs for a major CPU manufacturer (you've used them). She is responsible for physical design for one tile (there are many tiles, each of which has other physical designers). Her single tile, by itself, is substantially larger than almost all ASIC designs in the world today. At that scale, most of the standard FPGA design tools don't even work. Designing in that space is substantially different than FPGA or even ASIC design.

sliverstorm 13y ago
The third type after FPGA and ASIC, sometimes called "full custom". Related to ASIC, but distinct. http://en.wikipedia.org/wiki/Full_custom http://en.wikipedia.org/wiki/Full_custom