4 ms·
Just to clarify a bit: It takes time to go through combinational logic (AND and OR gates, etc.) and your clock has to go as slow as the slowest path to ensure t
by rcfox 13y ago
Just to clarify a bit: It takes time to go through combinational logic (AND and OR gates, etc.) and your clock has to go as slow as the slowest path to ensure that the signals are all correct at the same time. Registers are the start- and end-points of a combinational path, so placing a register in the critical path can increase your clock speed. However, that means that the data isn't available on the other side of the register until the next clock cycle.
- StringyBob 13y agoYes - Static Timing Analysis is used to work out worst likely timing (slowest/fastest delay) paths and check it runs at your target MHz For ASIC work there are a couple of tools used these days: http://www.cadence.com/products/mfg/tempus/pages/default.aspx http://www.cadence.com/products/mfg/tempus/pages/default.asp... http://www.synopsys.com/Tools/Implementation/SignOff/Pages/PrimeTime.aspx http://www.synopsys.com/Tools/Implementation/SignOff/Pages/P... Electronic Design Automation is a tough market to crack - for most startups the exit strategy is to be bought by one of the 2 (or 3) big players without being sued by them first!