3 ms·

> I believe the answer in this case is you latch the signal, and use a local copy. So the latch is local to both, and therefore not using a signal from another

by derleth 13y ago

> I believe the answer in this case is you latch the signal, and use a local copy. So the latch is local to both, and therefore not using a signal from another module?

sliverstorm 13y ago
The latch would be local to the module. The latch captures the input, and reproduces it inside the module. Think like this: sub proc { my $latch = @_[0]; } We capture the input signal in $latch for local use in the proc
- tcas 13y ago
  So, essentially feeding it into something like BUF? I thought those were optimized out on modern FPGAs. I can see the sourcing issue when trying to fan out too much from a single module, but I don't see any issue doing a high speed interconnect between them as long as you're intelligent about where the modules are going to be placed in regards to chip I/O. i.e. don't have a high speed serdes unit on one bank try and directly talk to a bank on the other side of a chip.
  - sliverstorm 13y ago
    I don't remember what a BUF represents in FPGA tools- the name implies an inverter pair, e.g. buffer, but I don't remember for sure. Anyway, I mean a sequential element, such as a latch or a flip-flop. (If you don't know what those are, please pay a quick visit to Wikipedia- they are fundamental) It is a placement/distance problem. Sometimes one module needs to talk to a module on the other side of the chip, and there's no two ways about it. In that case, when you clock it fast enough, you need to break the path across cycles. edit: It looks like BUF is indeed the Xilinx primitive for a buffer, so no. Definitely not what I meant. Half-cocked Example: module test ( a, clk ); input a; input clk; wire a; wire clk; reg flop; always @ (posedge clk) begin flop = a; end (... useful things ...) endmodule
    - jnbiche 13y ago
      I'm curious: you're discussing FPGAs with someone who knows enough about them to know the Xilinx instruction set. Why would you think that he/she might not know what a flip-flop is?
      - sliverstorm 13y ago
        Because tcas thought when I said "latch" that I might meant "buf"

by derleth 13y ago

> I believe the answer in this case is you latch the signal, and use a local copy. So the latch is local to both, and therefore not using a signal from another module?

sliverstorm 13y ago

The latch would be local to the module. The latch captures the input, and reproduces it inside the module. Think like this: sub proc { my $latch = @_[0]; } We capture the input signal in $latch for local use in the proc

tcas 13y ago
So, essentially feeding it into something like BUF? I thought those were optimized out on modern FPGAs. I can see the sourcing issue when trying to fan out too much from a single module, but I don't see any issue doing a high speed interconnect between them as long as you're intelligent about where the modules are going to be placed in regards to chip I/O. i.e. don't have a high speed serdes unit on one bank try and directly talk to a bank on the other side of a chip.
- sliverstorm 13y ago
  I don't remember what a BUF represents in FPGA tools- the name implies an inverter pair, e.g. buffer, but I don't remember for sure. Anyway, I mean a sequential element, such as a latch or a flip-flop. (If you don't know what those are, please pay a quick visit to Wikipedia- they are fundamental) It is a placement/distance problem. Sometimes one module needs to talk to a module on the other side of the chip, and there's no two ways about it. In that case, when you clock it fast enough, you need to break the path across cycles. edit: It looks like BUF is indeed the Xilinx primitive for a buffer, so no. Definitely not what I meant. Half-cocked Example: module test ( a, clk ); input a; input clk; wire a; wire clk; reg flop; always @ (posedge clk) begin flop = a; end (... useful things ...) endmodule
  - jnbiche 13y ago
    I'm curious: you're discussing FPGAs with someone who knows enough about them to know the Xilinx instruction set. Why would you think that he/she might not know what a flip-flop is?
    - sliverstorm 13y ago
      Because tcas thought when I said "latch" that I might meant "buf"