Yes, ARMv8 has twice as many architectural GPRs and NEON/FP registers, but: 1. This has nothing to do with 64-bitness, it could just as easily have been applie

Yes, ARMv8 has twice as many architectural GPRs and NEON/FP registers, but: 1. This has nothing to do with 64-bitness, it could just as easily have been applied to a 32-bit iteration of the ARM ISA. (You're not saying it does, but many, including the linked article, do.) Widening the GPRs to 64-bits means that the number of bits of architectural register space is actually quadrupled (there are 2x as many, each of which is 2x as wide). 2. Performance scales (very) sublinearly with the number of available architectural registers. 3. The number of physical registers in the microarchitectural implementation may be unchanged, or may even be lower, than any given implementation of ARMv7. It is unlikely that this "Swift 2" core has fewer physical registers than the A6's "Swift 1", but ARMv8 just sets a higher lower-bound on the number of physical registers, and makes it modestly easier for a compiler to express a given piece of code with fewer spills. In reality, the number of physical GPRs in Swift 1 was likely already >= 32 due to register renaming (https://en.wikipedia.org/wiki/Register_renaming https://en.wikipedia.org/wiki/Register_renaming).