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From Wikipedia: "Originally, Verilog was intended to describe and allow simulation; only afterwards was support for synthesis added." http://en.wikipedia.org/
by jonmrodriguez 13y ago
From Wikipedia:
"Originally, Verilog was intended to describe and allow simulation; only afterwards was support for synthesis added."
http://en.wikipedia.org/wiki/Verilog#History http://en.wikipedia.org/wiki/Verilog#History