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I'm having a hard time reading this article, considering he starts off with false information like: "The problem is that Verilog was originally designed as a l
by rootlocus 13y ago
I'm having a hard time reading this article, considering he starts off with false information like:
"The problem is that Verilog was originally designed as a language to describe simulations, so it has constructs to describe arbitrary interactions between events. When X transitions from 0 to 1, do Y. [...] But then someone had the bright idea of using Verilog to represent hardware."
Verilog was made from the start with the sole intention of describing hardware. Hardware programming and software programming are fundamentally different. Comparing them is irrelevant.
- jonmrodriguez 13y agoFrom Wikipedia: "Originally, Verilog was intended to describe and allow simulation; only afterwards was support for synthesis added." http://en.wikipedia.org/wiki/Verilog#History http://en.wikipedia.org/wiki/Verilog#History