IMO the syntax of Verilog isn't so problematic. Adhering to a simple style guide will avoid most gotchas. The author does make a passing reference to the real p

IMO the syntax of Verilog isn't so problematic. Adhering to a simple style guide will avoid most gotchas. The author does make a passing reference to the real problems though: 1. Simulation is many orders of magnitude slower than the same code running in production (and you see code in production only after many months and dollars). You don't face this slowdown when writing software. 2. Compared to software, there is much less code reuse in hardware. With software, it doesn't cost much if your binary is 10% or even 100% bigger, so your class can be written a more general/reusable but less efficient way. But a 10% increase in the size of a chip makes it significantly more expensive, so as a hardware designer you tend to create one-off 'classes' that are as efficient as possible, but less general/reusable.