3 ms·

By far, most of my time spent in FPGA dev so far has been envisioning the state machines and timing details involved. I use VHDL, so it's never been a question

By far, most of my time spent in FPGA dev so far has been envisioning the state machines and timing details involved. I use VHDL, so it's never been a question of "how can I make VHDL output what I want?"---for me, it's always the struggle of "why can't I just ask VHDL to make n of these units?", where n is some upstream provided number. I think the author might need to step away and look at it from the other side: how can we take a working, but overly-verbose language like VHDL and make it more powerful? At least VHDL was envisioned from the beginning as a hardware description language, and it definitely shows.

DigitalJack 13y ago
Generate statements are your friend.
- cyanoacry 13y ago
  VHDL generics and generate work nicely for 1d cases, but for 2d cases (systolic arrays), it's difficult to make the scripting really work without hard-coding a bunch of corner cases. Another example is that defining barrel shifters is impossible to parameterize, because you need to hardcode the mux cases (see the Xilinx datasheet[1]). That's kind of insane, considering that bit-shifting is a very common and basic operation. This is particularly problematic if you're trying to describe something without having to resort to platform-specific instantiation blocks. It's a little frustrating that VHDL doesn't have a higher-level standard instantiation library, because you're chained to a platform the moment you start doing anything other than basic flip-flops. [1] http://www.xilinx.com/support/sw_manuals/2_1i/download/xsisyn.pdf http://www.xilinx.com/support/sw_manuals/2_1i/download/xsisy... (pg 51)
  - DigitalJack 13y ago
    Well, I suppose you could say assembly is an analog of writing hdl that is very structural. I haven't done it myself, but generates can be nested. You'd have to check to see if your tools support it or not though. With the xilinx example, I'm not sure what you mean. Is it choosing to do multi-level muxing vs a naive muxing solution? I'd start by just writing a simple behavioral version, and only if that didn't meet performance constraints would I bother doing anything structural about it. It's late and maybe I'm just not thinking it through. I'll take a stab at some of this and maybe it'll be clearer to me.
  - ta_vhdl 13y ago
    Why not using a higher level language like confluence, or some other tool which help you generate the verilog boilerplate for this kind of situation?

DigitalJack 13y ago

Generate statements are your friend.

cyanoacry 13y ago
VHDL generics and generate work nicely for 1d cases, but for 2d cases (systolic arrays), it's difficult to make the scripting really work without hard-coding a bunch of corner cases. Another example is that defining barrel shifters is impossible to parameterize, because you need to hardcode the mux cases (see the Xilinx datasheet[1]). That's kind of insane, considering that bit-shifting is a very common and basic operation. This is particularly problematic if you're trying to describe something without having to resort to platform-specific instantiation blocks. It's a little frustrating that VHDL doesn't have a higher-level standard instantiation library, because you're chained to a platform the moment you start doing anything other than basic flip-flops. [1] http://www.xilinx.com/support/sw_manuals/2_1i/download/xsisyn.pdf http://www.xilinx.com/support/sw_manuals/2_1i/download/xsisy... (pg 51)
- DigitalJack 13y ago
  Well, I suppose you could say assembly is an analog of writing hdl that is very structural. I haven't done it myself, but generates can be nested. You'd have to check to see if your tools support it or not though. With the xilinx example, I'm not sure what you mean. Is it choosing to do multi-level muxing vs a naive muxing solution? I'd start by just writing a simple behavioral version, and only if that didn't meet performance constraints would I bother doing anything structural about it. It's late and maybe I'm just not thinking it through. I'll take a stab at some of this and maybe it'll be clearer to me.
- ta_vhdl 13y ago
  Why not using a higher level language like confluence, or some other tool which help you generate the verilog boilerplate for this kind of situation?