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This amounts to using your x86 CPU as an OISC [1], more specifically, as one with a transport triggered architecture [2]. -- Edit: I wrote a tiny TTA CPU simu

This amounts to using your x86 CPU as an OISC [1], more specifically, as one with a transport triggered architecture [2]. -- Edit: I wrote a tiny TTA CPU simulator to better understand the concept when I first encountered it back in 2006. I recently discovered its code in a old backup and this story has prompted me to upload it; here it is: https://bitbucket.org/networked/oisc-sim https://bitbucket.org/networked/oisc-sim. The code is ugly in places and lacks comments but it still might be easier to get started with than x86 assembly. The simulator has the command syntax of REG1 REG2 where both REG1 and REG2 are register numbers. This transfers the contents of REG1 to REG2. By default all registers contain unsigned int values. There are registers that are mapped to the sum, difference, product, etc. of registers 0 and 1; that's how you do arithmetic and comparisons. Flow control is accomplished by moving the desired instruction number to REG_PC (register 3). Input and output (numerical only) is done by moving data to and from REG_IO (register 4). To store a literal move its value to REG_CONST (register 11; you can then move it to whatever register you like from there). If you find yourself short on registers increase REGS_N to, say, 256 in mov-rev.c. Because it's easy to get lost in the register numbers a sample factorial program I've included (https://bitbucket.org/networked/oisc-sim/src/3b3903518033494476ad10f4f3eb0d0bf59166b6/fact.oisc?at=master https://bitbucket.org/networked/oisc-sim/src/3b3903518033494...) uses the C preprocessor to assign them names. Download the simulator and type make fact to try it. It'll ask you to input a single number followed by the <enter> key. There's no documentation to speak of but you can get a dynamically generated special register reference by running mov-rev -h [1] https://en.wikipedia.org/wiki/One_instruction_set_computer https://en.wikipedia.org/wiki/One_instruction_set_computer [2] https://en.wikipedia.org/wiki/Transport_triggered_architecture https://en.wikipedia.org/wiki/Transport_triggered_architectu...

tekacs 13y ago
From the paper: > Finding Turing-completeness in unlikely places has long been a pastime of bored computer scientists. The number of bizarre ma- chines that have been shown Turing-complete is far too great to describe them here, but a few resemble what this paper describes. > ... [several examples] ... > A single instruction machine using only MOVE was described by Douglas W. Jones [1], where Turing-completeness is gained by having memory-mapped arithmetic and logic units (so that other operations can be performed by moving data a predefined memory location and collecting the result afterwards). Some machines based on this principle have been built, and are generally known as “move machines” or “transport-triggered architectures”. Also: > Removing all but the mov instruction from future iterations of the x86 architecture would have many advantages: the instruction format would be greatly simplified, the expensive decode unit would become much cheaper, and silicon currently used for complex functional units could be repurposed as even more cache. As long as someone else implements the compiler. :)
- ibrahima 13y ago
  > > Removing all but the mov instruction from future iterations of the x86 architecture would have many advantages: the instruction format would be greatly simplified, the expensive decode unit would become much cheaper, and silicon currently used for complex functional units could be repurposed as even more cache. As long as someone else implements the compiler. I realize it's tongue in cheek, but saying the decode unit in x86 is expensive is kind of a tired and untrue adage in today's computer architecture terms. But I guess it is fair to say that the die is stuffed with as much cache as they can fit :)
  - duaneb 13y ago
    It may not be accurate to say "decode unit" anymore but who wouldn't welcome anything removing the large amounts of cruft from the ISA? Nobody uses most of the damn opcode space except where required for mode trickery or legacy code.

tekacs 13y ago

From the paper: > Finding Turing-completeness in unlikely places has long been a pastime of bored computer scientists. The number of bizarre ma- chines that have been shown Turing-complete is far too great to describe them here, but a few resemble what this paper describes. > ... [several examples] ... > A single instruction machine using only MOVE was described by Douglas W. Jones [1], where Turing-completeness is gained by having memory-mapped arithmetic and logic units (so that other operations can be performed by moving data a predefined memory location and collecting the result afterwards). Some machines based on this principle have been built, and are generally known as “move machines” or “transport-triggered architectures”. Also: > Removing all but the mov instruction from future iterations of the x86 architecture would have many advantages: the instruction format would be greatly simplified, the expensive decode unit would become much cheaper, and silicon currently used for complex functional units could be repurposed as even more cache. As long as someone else implements the compiler. :)

ibrahima 13y ago
> > Removing all but the mov instruction from future iterations of the x86 architecture would have many advantages: the instruction format would be greatly simplified, the expensive decode unit would become much cheaper, and silicon currently used for complex functional units could be repurposed as even more cache. As long as someone else implements the compiler. I realize it's tongue in cheek, but saying the decode unit in x86 is expensive is kind of a tired and untrue adage in today's computer architecture terms. But I guess it is fair to say that the die is stuffed with as much cache as they can fit :)
- duaneb 13y ago
  It may not be accurate to say "decode unit" anymore but who wouldn't welcome anything removing the large amounts of cruft from the ISA? Nobody uses most of the damn opcode space except where required for mode trickery or legacy code.