3 ms·

It's fortunate, since it made Intel able to encode the new XACQUIRE/XRELEASE of the Transactional Synchronization Extensions' Hardware Lock Elision using these

It's fortunate, since it made Intel able to encode the new XACQUIRE/XRELEASE of the Transactional Synchronization Extensions' Hardware Lock Elision using these short ancient prefixes: "Hardware Lock Elision adds two new instruction prefixes XACQUIRE and XRELEASE. These two prefixes reuse the opcodes of the existing REPNE/REPE prefixes (F2H/F3H). On processors that do not support TSX, REPNE/REPE prefixes are ignored on instructions for which the XACQUIRE/XRELEASE are valid, thus enabling backward compatibility." from http://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions#Hardware_Lock_Elision http://en.wikipedia.org/wiki/Transactional_Synchronization_E...

kps 13y ago
And REPNE RET, among others, similarly has an interpretation in Intel® Memory Protection Extensions (lawyers made me write that) to help make the new pointer bounds checking ABI transparent & interoperable with other code. [1] http://software.intel.com/en-us/articles/introduction-to-intel-memory-protection-extensions http://software.intel.com/en-us/articles/introduction-to-int... [2] http://download-software.intel.com/sites/default/files/319433-015.pdf http://download-software.intel.com/sites/default/files/31943...