4 ms·Is there any plans to work hardware transactional memory into the mix?by kazagistar 13y agoIs there any plans to work hardware transactional memory into the mix?kingkilr 13y agoCurrent HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.4buser 13y agoEven new Intel Haswell's STM?sanxiyn 13y agoYes, Intel TSX too has a limited transaction size.