Heat dissipation and manufacturing concerns aside, a 3D stacked architecture seems to be the most obvious thing to increase clock speeds. Light can only travel

Heat dissipation and manufacturing concerns aside, a 3D stacked architecture seems to be the most obvious thing to increase clock speeds. Light can only travel about 30cm every nanosecond: components clocked at 4GHz can't be more than 7.5cm apart from each other (I think -- and probably have to be quite a bit less for practical concerns). Packing everything vertically makes it easier to keep these propagation delays low and drive up clock speeds. We seem to be in a race to the smallest transistor physically possible, to increase density on 2D chips. Tiny transistors generally leak more heat due to quantum tunnelling, right? So what if the industry moved toward much, much more efficient, larger transistors, layered hundreds or thousands of layers thick in a large 3D architecture? I think the only reason this isn't happening is because it's not really possible to manufacture that sort of chip without it taking a thousand times as long and being a thousand times as likely to fail QA -- but maybe this is a step in that direction.