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not being a chip engineer, i wonder while 3D chip layer stacking isn't in the wide use. For high powered chips it is understandable because of heat dissipation

not being a chip engineer, i wonder while 3D chip layer stacking isn't in the wide use. For high powered chips it is understandable because of heat dissipation requirements. Whereis for lower powered it may seem that additional layers of heat transfer material between working layers would do the trick. For CPUs the 3D stacking would decrease distances between various parts for example and would allow something like cluster (of low powered chips) in a cube.

jlgreco 13y ago
For low power chips, what advantages would there be for stacking? My thought is that low power chips probably aren't going for performance (since they are low power), so stacking for performance wouldn't really be buying them anything necessary. Maybe you could just get smaller form-factor low power chips.
- VladRussian2 13y ago
  half of motivation for 3D i see is the model of the brain, not the actual geometry of the brain, which is about 2D+ (don't remember the fractal dimension value of the brain), more a logical model of it where computational power comes from having number of connection an order of magnitude larger than number of connected neurons. Our current electronics has it backwards - number of connection is orders of magnitude less than number of connected elements. 3D seems like a way to build computational devices with increased number of connections (that though requires some work on software side as well to benefit from it)
wmf 13y ago
Stacking is pretty expensive (especially TSVs), so it's kind of a last resort when cost is no object.
revelation 13y ago
I guess its just the complicated production method? How does lithography work with this vertical stacking?
ChuckMcM 13y ago
[Disclaimer, the last time I stepped into a chip fab it was 1998] There were (and may still be) several reasons that 3D was not a regular technology in use. The first was that connecting transistors "across" the chip was done using a metal layer (aluminium at first, later copper) and laying down a metal layer left forced a distance between it and the next silicon layer that you would end up bridging with poly-silicon (NP doped silicon so that it conducts electricity but not as well as metal does). So all of the cross layer connects that weren't metal were slow. Heat dissipation was another issue for transistors between a 'top' and 'bottom' layer. Varying feature height, so if transistors were 3 uM thick and resistors were 1uM thick then you put a transistor above a resistor its drain and source layers would be 1uM up from the plane in which the other transistor sits. Process contamination, basically building a transistor on top of a surface of SIO2 was one thing, but building it on top of another transistor meant than your ion implanting step needed to have really accurate control of depth. The MEMS revolution gave people a lot more tools that were accurate in depth (vs X & Y position) and regular feature patterns (as opposed to general purpose logic) lend themselves to better 3D planning. One of Intel's big breakthroughs in 22nM chips was its tri-gate vertical transistor design [1] which allowed the gate area of the transistor to be vertical and thus have enough silicon to hold a reasonable number of electrons. [1] http://newsroom.intel.com/docs/DOC-2032 http://newsroom.intel.com/docs/DOC-2032
jpmattia 13y ago
> not being a chip engineer, i wonder while 3D chip layer stacking isn't in the wide use. Short version: The process to make a 2D layer of transistors requires something like 20-30 masking steps, and many of those steps require significant heating. Adding a second plane of 2D transistors on top subjects all of the transistors underneath to more heating, so it is hard to build that structure on top without making the transistors underneath nonfunctional.

jlgreco 13y ago

For low power chips, what advantages would there be for stacking? My thought is that low power chips probably aren't going for performance (since they are low power), so stacking for performance wouldn't really be buying them anything necessary. Maybe you could just get smaller form-factor low power chips.

VladRussian2 13y ago
half of motivation for 3D i see is the model of the brain, not the actual geometry of the brain, which is about 2D+ (don't remember the fractal dimension value of the brain), more a logical model of it where computational power comes from having number of connection an order of magnitude larger than number of connected neurons. Our current electronics has it backwards - number of connection is orders of magnitude less than number of connected elements. 3D seems like a way to build computational devices with increased number of connections (that though requires some work on software side as well to benefit from it)

wmf 13y ago

Stacking is pretty expensive (especially TSVs), so it's kind of a last resort when cost is no object.

revelation 13y ago

I guess its just the complicated production method? How does lithography work with this vertical stacking?

ChuckMcM 13y ago

[Disclaimer, the last time I stepped into a chip fab it was 1998] There were (and may still be) several reasons that 3D was not a regular technology in use. The first was that connecting transistors "across" the chip was done using a metal layer (aluminium at first, later copper) and laying down a metal layer left forced a distance between it and the next silicon layer that you would end up bridging with poly-silicon (NP doped silicon so that it conducts electricity but not as well as metal does). So all of the cross layer connects that weren't metal were slow. Heat dissipation was another issue for transistors between a 'top' and 'bottom' layer. Varying feature height, so if transistors were 3 uM thick and resistors were 1uM thick then you put a transistor above a resistor its drain and source layers would be 1uM up from the plane in which the other transistor sits. Process contamination, basically building a transistor on top of a surface of SIO2 was one thing, but building it on top of another transistor meant than your ion implanting step needed to have really accurate control of depth. The MEMS revolution gave people a lot more tools that were accurate in depth (vs X & Y position) and regular feature patterns (as opposed to general purpose logic) lend themselves to better 3D planning. One of Intel's big breakthroughs in 22nM chips was its tri-gate vertical transistor design [1] which allowed the gate area of the transistor to be vertical and thus have enough silicon to hold a reasonable number of electrons. [1] http://newsroom.intel.com/docs/DOC-2032 http://newsroom.intel.com/docs/DOC-2032

jpmattia 13y ago

> not being a chip engineer, i wonder while 3D chip layer stacking isn't in the wide use. Short version: The process to make a 2D layer of transistors requires something like 20-30 masking steps, and many of those steps require significant heating. Adding a second plane of 2D transistors on top subjects all of the transistors underneath to more heating, so it is hard to build that structure on top without making the transistors underneath nonfunctional.