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Samsung Starts Mass Producing Industry’s First 3D Vertical NAND Flash
- ChuckMcM 13y agoPretty amazing hack to get around the size limitations of NAND flash feature size.
- ihsw 13y agoI wonder how long it'll take for Apple to violate Samsung's patents, when product bans will be proposed, and when those bans get overturned.
- wtallis 13y agoThat's not funny. This isn't the market where Apple and Samsung compete, it's the market where Apple is a huge Samsung customer, where a few years ago Apple was responsible for an outright majority of Samsung's sales.
- dba7dba 13y agoWhere did you get that number? During the last few years, Apple provided about 3% - 8% of annual revenue of Samsung Group as a whole. Samsung Group is huge. Their Samsung electronics is huge but so are other groups. Samsung Shipyard is building 2 floating natural gas plants, each costing One Billion US dollars.
- revelation 13y agoSamsung is a gigantic company, a South Korean Siemens. They are active in any number of markets, and Apple certainly didn't provide for a majority of their sales.
- wtallis 13y agoRead my comment again. I wasn't making any statements about the Samsung conglomerate as a whole. I was only discussing the flash memory market, and in that market, Apple was indeed responsible at one time for purchasing more than 50% of Samsung's production of flash memory (this was during the heyday of the iPod Nano and prior to mainstream SATA SSDs).
- dba7dba 13y agoWell you didn't say Samsung Electronics or Samsung Semiconductor. Nor mention Flash Memory. And Samsung Electronics makes a lot more than just Flash memory.
- makomk 13y agoRumour has it Apple have been trying to move away from Samsung for components, though.
- mullingitover 13y agoI doubt the patents for this are going to end up in a standard that forces Samsung to license them under FRAND terms.
- kenster07 13y agoThis is incredible and may have far reaching implications for computing. Hopefully, the cost ratios haven't disproportionately increased as well.
- VladRussian2 13y agonot being a chip engineer, i wonder while 3D chip layer stacking isn't in the wide use. For high powered chips it is understandable because of heat dissipation requirements. Whereis for lower powered it may seem that additional layers of heat transfer material between working layers would do the trick. For CPUs the 3D stacking would decrease distances between various parts for example and would allow something like cluster (of low powered chips) in a cube.
- jlgreco 13y agoFor low power chips, what advantages would there be for stacking? My thought is that low power chips probably aren't going for performance (since they are low power), so stacking for performance wouldn't really be buying them anything necessary. Maybe you could just get smaller form-factor low power chips.
- VladRussian2 13y agohalf of motivation for 3D i see is the model of the brain, not the actual geometry of the brain, which is about 2D+ (don't remember the fractal dimension value of the brain), more a logical model of it where computational power comes from having number of connection an order of magnitude larger than number of connected neurons. Our current electronics has it backwards - number of connection is orders of magnitude less than number of connected elements. 3D seems like a way to build computational devices with increased number of connections (that though requires some work on software side as well to benefit from it)
- wmf 13y agoStacking is pretty expensive (especially TSVs), so it's kind of a last resort when cost is no object.
- revelation 13y agoI guess its just the complicated production method? How does lithography work with this vertical stacking?
- ChuckMcM 13y ago
- burke 13y agoHeat dissipation and manufacturing concerns aside, a 3D stacked architecture seems to be the most obvious thing to increase clock speeds. Light can only travel about 30cm every nanosecond: components clocked at 4GHz can't be more than 7.5cm apart from each other (I think -- and probably have to be quite a bit less for practical concerns). Packing everything vertically makes it easier to keep these propagation delays low and drive up clock speeds. We seem to be in a race to the smallest transistor physically possible, to increase density on 2D chips. Tiny transistors generally leak more heat due to quantum tunnelling, right? So what if the industry moved toward much, much more efficient, larger transistors, layered hundreds or thousands of layers thick in a large 3D architecture? I think the only reason this isn't happening is because it's not really possible to manufacture that sort of chip without it taking a thousand times as long and being a thousand times as likely to fail QA -- but maybe this is a step in that direction.
- svantana 13y agoWell there is quantum tunneling but there is also dennard scaling, so it goes both ways. Transistors need to be small but also non-leaky, so that's why everyone's toying around with exotic materials and structures.
- rwallace 13y agoThe article mentions 10nm process size, whereas I thought the current state-of-the-art was 20nm. Is flash memory an exception? And if so, does that also apply to DRAM? Or am I just confused?
- makomk 13y agoFlash and DRAM have highly regular structures, which means they tend to be ahead of everything else in terms of feature size (and also, feature size isn't an exact measurement anyway).
- mvgoogler 13y agoThe press-release said 10nm _class_ with a big asterisk next to it. I would be willing to bet that means something like 19nm.
- BariumBlue 13y ago>128 gigabit (Gb) [per chip] This is the first I think I've seen size measured in gigabits, rather than gigabytes, of which there'd be 16, which is still impressive, but on amazon I can buy a 32GB sdcard for $20.
- mvgoogler 13y agoFlash chips are typically spec'd in terms of bits in the industry. Things like SD cards are really small consumer electronics devices and are spec'd in terms of bytes.