4 ms·

If they manage to depress the cost-to-orbit sufficiently, they'll maybe be able to take more shielding along. It might even be dual-use stuff like carefully pl

by shabble 13y ago

If they manage to depress the cost-to-orbit sufficiently, they'll maybe be able to take more shielding along. It might even be dual-use stuff like carefully placed water tanks or stacks of prefab building materials, which can then be used on the journey or at the destination. On the hardening ICs specifically, I recall that SOI is potentially a better performing technology than bulk silicon wafers, the actual performance drop is due to much larger feature sizes to better handle low-energy rad strikes. I suspect (but haven't looked in a long time) that the performance could be radically improved if they could develop the process to modern equivalents, but the economics just aren't there. I was just wondering if it would be possible to use ECC on the core internals rather than just the RAM, and it looks like someone has considered it for the register file[1] I suppose it might be useful on the instruction pipeline as well, and other places. Then again, it may be just easier all round to take the SpaceX current approach of many simple cores, and redundancy in software. [1] http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4708869 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4708869

kristoffer 13y ago
The register file and cache is typically protected with some kind of ECC. The other parts of the CPU are protected by using rad hard flip flops (be it either TMR or other means). But this is the road SpaceX is not taking ... And all these techniques only protect against soft errors. I was more interested in how to mitigate against permanent errors (latchup) and tolerating high total dose when using commercial components. Will they do this by screening components which are manufactured using potential good fabrication process e.g. SOI.
- XorNot 13y ago
  It seems like if they can on average use smaller parts and more of them, then it just comes down to statistics - permanent chip damage isn't impossible in rad-hard electronics, just less likely. I suspect it'll come down to a test though - at some SpaceX are going to launch an unmanned Dragon to Mars, and that will be more then anything a fascinating exercise in really understanding the deep space radiation environment, which we still do not know nearly enough about.

by shabble 13y ago

kristoffer 13y ago

The register file and cache is typically protected with some kind of ECC. The other parts of the CPU are protected by using rad hard flip flops (be it either TMR or other means). But this is the road SpaceX is not taking ... And all these techniques only protect against soft errors. I was more interested in how to mitigate against permanent errors (latchup) and tolerating high total dose when using commercial components. Will they do this by screening components which are manufactured using potential good fabrication process e.g. SOI.

XorNot 13y ago
It seems like if they can on average use smaller parts and more of them, then it just comes down to statistics - permanent chip damage isn't impossible in rad-hard electronics, just less likely. I suspect it'll come down to a test though - at some SpaceX are going to launch an unmanned Dragon to Mars, and that will be more then anything a fascinating exercise in really understanding the deep space radiation environment, which we still do not know nearly enough about.