Some ideas (at least on x86): - alignment greater than 16-bytes, eg. 128 bytes for isolated buffers. - the hardware prefetcher like to load cachelines around

Some ideas (at least on x86): - alignment greater than 16-bytes, eg. 128 bytes for isolated buffers. - the hardware prefetcher like to load cachelines around the memory actually accessed, just in case. So data chunks that will be accessed at the same time better be near each other to save cache usage a bit. - memory access which does not have a simple pattern is slower than one which is contiguous or have a simple stride.