4 ms·

I never got why cmov was 2 µops (and thus 2 cycle latency) on Intel CPUs. On AMD (and modern ARM), it's 1 µop with 1 cycle latency and can be issued to any ALU.

by brigade 13y ago

I never got why cmov was 2 µops (and thus 2 cycle latency) on Intel CPUs. On AMD (and modern ARM), it's 1 µop with 1 cycle latency and can be issued to any ALU. Which makes it a win for a single conditional mov in pretty much anything short of microbenchmarks with 100% predictable branches, as in Linus's test case. Also setcc is abysmally stupid in leaving the high 3/7 bytes of the register unmodified - what were Intel's engineers smoking?

rayiner 13y ago
A lot of features of Intel CPUs can be explained by the fact that the Pentium Pro (and basically every Intel CPU after that until I believe Sandy Bridge), uses a basic architecture that supports reading only two input operands for each instruction in a single cycle. CMOV has to read the flags register, the source register, and the old value of the destination register. See: http://newsgroups.derkeiler.com/Archive/Comp/comp.arch/2013-04/msg00093.html http://newsgroups.derkeiler.com/Archive/Comp/comp.arch/2013-....
cwzwarich 13y ago
Intel has traditionally limited the number of inputs to a uop to 2, although in their more recent microarchitectures with macro-op fusion the fused uops can take 3 inputs. This is a tradeoff in the design of the frontend, since having fewer dependencies per uop simplifies the design and improves area, timing and power.
pbsd 13y ago
> Also setcc is abysmally stupid in leaving the high 3/7 bytes of the register unmodified - what were Intel's engineers smoking? It makes sense in context. When the instruction was introduced, it made sense to have 8-bit flags instead of overwriting a whole register (remember you only have 7, and we're usually optimizing things for size at this point). You can also do SETcc of the upper 8 bits of a 16-bit register, e.g. SETNZ AH. It doesn't make sense now, true, but I've never seen it as a large annoyance; you can avoid using SETcc in favor of full-register instructions (excluding CMOV) most of the time anyway.

by brigade 13y ago

rayiner 13y ago

A lot of features of Intel CPUs can be explained by the fact that the Pentium Pro (and basically every Intel CPU after that until I believe Sandy Bridge), uses a basic architecture that supports reading only two input operands for each instruction in a single cycle. CMOV has to read the flags register, the source register, and the old value of the destination register. See: http://newsgroups.derkeiler.com/Archive/Comp/comp.arch/2013-04/msg00093.html http://newsgroups.derkeiler.com/Archive/Comp/comp.arch/2013-....

cwzwarich 13y ago

Intel has traditionally limited the number of inputs to a uop to 2, although in their more recent microarchitectures with macro-op fusion the fused uops can take 3 inputs. This is a tradeoff in the design of the frontend, since having fewer dependencies per uop simplifies the design and improves area, timing and power.

pbsd 13y ago

> Also setcc is abysmally stupid in leaving the high 3/7 bytes of the register unmodified - what were Intel's engineers smoking? It makes sense in context. When the instruction was introduced, it made sense to have 8-bit flags instead of overwriting a whole register (remember you only have 7, and we're usually optimizing things for size at this point). You can also do SETcc of the upper 8 bits of a 16-bit register, e.g. SETNZ AH. It doesn't make sense now, true, but I've never seen it as a large annoyance; you can avoid using SETcc in favor of full-register instructions (excluding CMOV) most of the time anyway.