4 ms·
Let me be clear - obviously this is discussing a logical CPU not the actual ISA. My point is just that the linux doc illustrates the minimum guarantees for how
by codemac 13y ago
Let me be clear - obviously this is discussing a logical CPU not the actual ISA.
My point is just that the linux doc illustrates the minimum guarantees for how Linux approaches these issues, which given a ACQUIRE/RELEASE instruction in x86 and load/store ordering, is probably going to be pretty accurate for the state of successful lock execution behavior in the more general sense.
- signa11 13y ago> obviously this is discussing a logical CPU not the actual ISA. being a tad pedantic here, but shouldn't this be a part of the machine's micro-arch rather than the isa ?
- codemac 13y agoWell, the LOCK discussion in the linux docs I linked could be a bit vague, because there is also the x86 "lock" instruction. I was talking about how lock worked in linux, which could be implemented using lock+addl, or xchg, etc. The TSX HLE stuff (xacquire/xrelease) are precisely what that document doesn't cover. So it's a bit convoluted. I was talking about micro-arch + linux implementation, and how it invalidates TFA's assumption of speculative execution. The documentation talks about micro-arch, but could be mistaken for discussing the ISA. So you're right, the article is discussing the micro-arch(and the ISA inherently due to TSX), and the document I posted is only talking about micro-arch, but could be mistaken for ISA stuff (as per a private email I had with someone about the word LOCK)