4 ms·
It's definitely a chicken-and-egg problem. All I meant by my comment is that I can't see FPGAs taking off if people are stuck connecting together IP or using Ve
by alecdibble 13y ago
It's definitely a chicken-and-egg problem. All I meant by my comment is that I can't see FPGAs taking off if people are stuck connecting together IP or using Verilog/VHDL. It's just too low level.