Here's an article (not written by me, just found by using google) that has an example how the VHDL/Verilog compiler infers to use a dual-ported SRAM from code t

Here's an article (not written by me, just found by using google) that has an example how the VHDL/Verilog compiler infers to use a dual-ported SRAM from code that describes the behavior, including the bugs you'll encounter. http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/ http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/