Xilinx' block diagram shows the FPGA having direct access to both the peripheral bus and the memory bus, including the cache coherency port, so I'd guess you ca

Xilinx' block diagram shows the FPGA having direct access to both the peripheral bus and the memory bus, including the cache coherency port, so I'd guess you can transfer data to the ARM cores fairly fast (as fast as you can get something from dram into L2 cache).