3 ms·

There are some interesting reasons for that. When a lot of transistors in an integrated circuit all switch at the same time, it can cause the chip's power and

by elwin 13y ago

There are some interesting reasons for that. When a lot of transistors in an integrated circuit all switch at the same time, it can cause the chip's power and ground voltage levels to shift, relative to the circuit board's power and ground levels. The size of the difference depends on the inductance between the chip and board, i.e. the inductance of the chip's power and ground pins. Inductance can be minimized by connecting a lot of inductors in parallel. Lots of small pins are better than a few big ones. If the inductance is too high and the chip's power voltage falls below its ground voltage, this will randomize every storage element on the chip. The rule of thumb is that a third of the pins need to be power or ground.

astrodust 13y ago
You're implying it could be done if whatever load distribution and power condition that's done outside of the chip, which consists of a lot of analog components to help manage rapid changes in power consumption, could be somehow packaged inside the chip. So, in rough terms, the internals of a large-scale chip are not one big integrated circuit, but a large number of smaller modules that are massively interconnected, then? That rule of thumb seems to apply to only a particular class of chips. Wouldn't the number of pins be somehow proportional to the power draw, as at higher currents induction would become a more severe problem? It's just usually the case that more power-hungry chips have more pins, as the 2011 socket is for Intel's flagship CPUs, the 1155 ones more commodity-oriented. With the power voltage dropping below ground, that unless you had a floating ground, that'd be implying reverse flow of current, negative voltage, right? Or are you talking about a non-zero voltage ground? I'm not sure what the presumption is in real-world CPU design.
- elwin 13y ago
  > That rule of thumb seems to apply to only a particular class of chips. Wouldn't the number of pins be somehow proportional to the power draw, as at higher currents induction would become a more severe problem? I think it depends on the chip's speed. The problem is with rapid changes in current. Of course, higher currents can also have higher fluctuations. > With the power voltage dropping below ground, that unless you had a floating ground, that'd be implying reverse flow of current, negative voltage, right? Or are you talking about a non-zero voltage ground? Suppose the board's ground rail is 0 V and the power rail is at 12 V. The chip's ground voltage might bounce up to 9 and its power down to 8. It does cause reverse currents and other bad effects.
  - astrodust 13y ago
    Ah, so the ground gets pulled up and the power driven down. Thanks. This makes a lot more sense. I never thought Intel was doing something for no reason, but the reasoning wasn't obvious.

by elwin 13y ago

astrodust 13y ago

You're implying it could be done if whatever load distribution and power condition that's done outside of the chip, which consists of a lot of analog components to help manage rapid changes in power consumption, could be somehow packaged inside the chip. So, in rough terms, the internals of a large-scale chip are not one big integrated circuit, but a large number of smaller modules that are massively interconnected, then? That rule of thumb seems to apply to only a particular class of chips. Wouldn't the number of pins be somehow proportional to the power draw, as at higher currents induction would become a more severe problem? It's just usually the case that more power-hungry chips have more pins, as the 2011 socket is for Intel's flagship CPUs, the 1155 ones more commodity-oriented. With the power voltage dropping below ground, that unless you had a floating ground, that'd be implying reverse flow of current, negative voltage, right? Or are you talking about a non-zero voltage ground? I'm not sure what the presumption is in real-world CPU design.

elwin 13y ago
> That rule of thumb seems to apply to only a particular class of chips. Wouldn't the number of pins be somehow proportional to the power draw, as at higher currents induction would become a more severe problem? I think it depends on the chip's speed. The problem is with rapid changes in current. Of course, higher currents can also have higher fluctuations. > With the power voltage dropping below ground, that unless you had a floating ground, that'd be implying reverse flow of current, negative voltage, right? Or are you talking about a non-zero voltage ground? Suppose the board's ground rail is 0 V and the power rail is at 12 V. The chip's ground voltage might bounce up to 9 and its power down to 8. It does cause reverse currents and other bad effects.
- astrodust 13y ago
  Ah, so the ground gets pulled up and the power driven down. Thanks. This makes a lot more sense. I never thought Intel was doing something for no reason, but the reasoning wasn't obvious.