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Intel’s Long Awaited Return to the Memory Business
- marshray 13y agoNo matter how tightly integrated it is into the package, I'm skeptical that Intel integrated graphics with 128MB of DRAM is going to replace an Nvidia GT 650M with 1-2 GB of GDDR5.
- voidlogic 13y agoIntel started out targeting the low end discrete graphics solutions, now maybe they re just moving their way up the food chain. I'm actually more excited that the CPU has access to this cache too.
- gnoway 13y agoThe link will not load. This article is about the same thing, presumably: http://www.anandtech.com/show/6911/intels-return-to-the-dram-business-haswell-gt3e-to-integrate-128mb-edram http://www.anandtech.com/show/6911/intels-return-to-the-dram...
- Hoff 13y agoFor comparison purposes, Intel Itanium 9500 series Poulson-class processors have ~40 MB of on-chip cache, split among the L1 I&D, L2 and L3 caches.
- ippisl 13y agoIsn't it the wrong direction to go? With the price of memory chips about $1 per 265Mbyte, and technologies of integrating multiple chips with tons of connections and speed(2.5D and 3D integration) closing by, what's the point in offering 128MB at a price hike of $50 ?
- adsr 13y agoOn die cache is orders of magnitude faster than regular ram. I have always thought that more cache would be a sensible addition when a process shrink give more available real estate.
- marshray 13y agoSure but that's static RAM. DRAM has 50+ ns of latency no matter how close you put it to the chip. What they can do though is achieve more aggregate bandwidth without increasing package pin count. Perhaps this explains why Intel was willing to allow Ivy Bridge to have only half the memory bandwidth of the previous Sandy Bridge: just not that many (non-server) systems were ending up with the four DIMMs required for full bandwidth. So now they're integrating it into the package itself.
- sparky 13y ago> DRAM has 50+ ns of latency no matter how close you put it to the chip. This is not some fundamental law; it's entirely dependent on bitline and wordline capacitance (array size). For external DRAM chips, huge arrays make sense, and you end up with tens of ns of latency. In an eDRAM cache scenario, you use much smaller arrays, and in the case of the POWER7 L3, latency is more like 6ns (for row hits, of course).
- marshray 13y agoIt seems to me (you may know more about this than I do) that one can design a memory system to make latency for sequential addresses accesses arbitrarily small and this is mostly how (G)DDR(n) have improved overall performance. But random (row miss) accesses don't seem to have improved much. From early 1980's to early 2000's, DRAM latency went from 150 to 50 ns and has stayed around there since. That's 1-2 doublings of performance in that parameter in the last 30 years, compared to who-knows how many in transistor size and speed. Still, Intel knows what they're doing and I can see a place for (yet another) spot in the memory hierarchy before the CPU resort to off-package DRAM.